I'm designing a board for a client with some unusual constraints. My question is well illustrated with the following simplified example. Doughnut Board

Assume the positions of everything are fixed. Let's also assume a 4-layer board for simplicity. The outer layers are signal layers, and the inner layers are two planes for Power and GND.

As can be seen from the image, there is a large hole in the middle of the board. The board will transmit data at 16 MHz (wavelength ~18m) from the ADC to the "Master" board via a connector.

Is there any concern that digital signals leaving the ADC will return to the connector in both clockwise and counter-clockwise paths?

Would it be better to break the plane such that this cannot occur?

Some quick LTSpice with arbitrary simulation parameters seems to suggest that NOT breaking the loop is the way to go. As seen below, leaving the loop decreases the return's inductance since the two paths are essentially in parallel:

enter image description here

  • \$\begingroup\$ Current is lazy, current will want to return following the path it took. So assuming you have a solid GND plane and a solid PWR plane then you won't have a problem. \$\endgroup\$
    – user16222
    Oct 2, 2020 at 22:10

2 Answers 2


The way I would approach this problem is asking myself, "What is the max current on the PCB ground before the ADC would 'see' the voltage?". In other words, what is the lowest common mode voltage generated by the ground before the ADC is affected.

For a 16-bit measurement 76uV represents 1 bit for a 5V range on the ADC, so let's look at how much current on a PCB would be needed to 'see' it on an ADC.

Let's suppose the PCB is 1" wide and 5" long (a square inch of PCB is about 0.35mΩ of resistance) so 5 square inches would be about 1.76mΩ. (you can adjust the dimensions accordingly or use a PCB calculator to get a rough cut estimate of the resistance.

76uV/1.76mΩ = 43.2mA

Which is a substantial amount of current, for an analog design IMO. If you double the path around the circle, you get half the resistance. As far as inductive coupling to generate noise on a ground loop on a PCB, I would think you would have to have amps of current running around and within a few inches of the PCB to get mA on the PCB.

Also the inductance of the same 1" by 5" trace is more like 4nH, so coupling would be minimal, but this is frequency dependent. If that trace is doubled by forming a ground loop then the inductance would be cut in half, but then you get loop coupling.

The inductance of the cable will cause much larger problems for the common mode noise of the ADC than the PCB itself as the cable is likely to be larger than 1Ω and have mA of current running through it (which isn't a problem because the voltage reference (if you have one, or it is internal to the ADC) of the ADC will reference to the ground plane of the PCB and so will the ADC, so place the reference close to the ADC)

In short, don't worry about the ground loop of the PCB unless your running in a high magnetic \ high current environment. If you are running a 24 bit ADC, then you might want to dig into the minutiae. A 14-bit measurement, conversely would also be less to worry about it being affected by noise.

Is there any concern that digital signals leaving the ADC will return to the connector in both Clockwise and Counter-Clockwise paths? Would it be better to break the plane such that this cannot occur?

Yes, but not so much because of ground loops, it depends on if there are other loads on the board and where the reference is (if any) again you want this as close as possible to the ADC. If you have a voltage regulator, it would also be a good idea to place closely to the ADC.

It would be wise to break the PCB in two if you had switching loads, the return currents should not be able to cross under/across the ADC, so if there is a switching load, it might be wise to place it on the other side of the PCB and place a break in between the two.

  • 1
    \$\begingroup\$ Remember, it's the dynamic switching which dominates the actual current. Typically one wants to design to minimize the loop area such that supplies or signals take the same geometric path as their ground return. \$\endgroup\$ Oct 2, 2020 at 18:02
  • \$\begingroup\$ I thought about mentioning that, but it also depends on if one is trying to make an absolute DC measurement, in that case any current would be a problem. A relative measurement, yes only the switching current matters. \$\endgroup\$
    – Voltage Spike
    Oct 2, 2020 at 18:03

If there are higher frequency signal components (including fast rise times on otherwise lower frequency digital signals) then the primary concern with current loops is EMI, as well as EMC depending on the sensitivity and noise margin of our inputs regardless of the frequencies on our board (what we may radiate from the board or what we may pick up from external radiated signals). That is the real concern I believe and needs to be carefully considered. This factor is addressed by having ground and power planes in close vicinity of each other and all uninterrupted signal traces, which that hole should not impact. The worst implementation would be for power to be supplied on one side and return on the other, or routing signal traces similarly far from the grounds. This could be forced to occur if such a slice was erroneously put on the board with signal lines traversing it. From a 3D viewpoint, if the image planes are 10 mils away (for example) that hole has absolutely no impact.


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