I am looking at the following schematic where there is an LVDS to LVDS connection. The common mode and swing are a little different between the output and the input. See image below

I am use to seeing 100 ohm differential at the receiver. I understand that the common mode and swing are different, so I thought that the designer would do something like this: to change common mode and swing

Does anyone know how this termination is working?


  • \$\begingroup\$ It could be a correct source termination for some situations, or it could be a placeholder to permit the possibility of a source termination (or even overcurrent limitation) to be tuned later. \$\endgroup\$ Oct 2, 2020 at 18:19
  • \$\begingroup\$ Given the connected device is a Xilinx FPGA, you should look at their IO User's Guide. They often require non-standard terminations to convert between the totem-pole I/O's of the FPGA and a purely differential signal. \$\endgroup\$
    – The Photon
    Oct 2, 2020 at 19:04

2 Answers 2


In AC analysis, assuming a well decoupled power supply, then the VCC and GND point can be considered directly connected. You can then work out resistor values which give an overall termination impedance to match your requirements.

For DC however, the VCC and GND are not shorted, they have some voltage between them. The resistors act like potential dividers which will set the lines to a DC bias point. You can calculate using potential divider equations what that DC voltage will be.

Essentially the termination allows you to apply a DC bias to your lines, which is certainly useful in the case of AC coupled signalling schemes. By adjusting the resistor values to be asymmetric between P and N, you can also implement a fail-safe biasing mode, whereby if one or both lines are broken (connector unplugged?) there will be a differential voltage between the two lines which will ensure the receiver reads a 1 or 0 rather than undefined.

  • \$\begingroup\$ So wouldn't the voltage divider above 330 and 22 ohms give you a low common mode (.21V) than the ADC is looking for? (1.125 to 1.8V)? \$\endgroup\$
    – Matty
    Oct 2, 2020 at 19:39
  • \$\begingroup\$ @Matty The first and second circuits you show are not the same thing. The ADC one doesn't have resistors to ground as shown. \$\endgroup\$ Oct 2, 2020 at 21:09
  • \$\begingroup\$ Furthermore in the first image, the 330 resistors aren't installed (note the "NM" = Not Mounted, written beneath their values). At which point the 22R resistors in series act as an attenuator of (100/(100+2*22)). \$\endgroup\$ Oct 2, 2020 at 21:12
  • \$\begingroup\$ Hi Tom, can you please explain the equation you derived for attenuation? Is the 100 from the internal termination of the receiver? \$\endgroup\$
    – Matty
    Oct 2, 2020 at 23:59

Screenshot from National Semiconductors LVDS Owners Manual 3rd Edition Spring 2004

enter image description here

Your configuration is shown in the Figure 2.2 and the following Text has some explanation to it...

  • \$\begingroup\$ That is the termination that I am used to seeing as in the Second figure. I am asking about the lvds termination in the first figure. \$\endgroup\$
    – Matty
    Oct 3, 2020 at 16:54
  • \$\begingroup\$ external resistors are easier with large levels and currents... but internal or external is no real difference other than you do not want resistors in a chip. big analog structures... in most cases you have low resistor values external and some kOhm's internal \$\endgroup\$
    – schnedan
    Oct 3, 2020 at 18:18

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