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The part under consideration is UDA1334BTS - the DAC I use in my design.

Here's the typical connection diagram:

enter image description here

If the circuit is being powered off, and then quickly on, the Vref voltage does not get as low as 0.75 V to get part properly reset, and the consequence is DAC output powering up with some arbitrary voltage, causing click when external interface writes initial value of 0 to the DAC. I can not state if only analog part is guilty, or digital part is also involved.

Here's the related circuit:

enter image description here

We can see that charge to the reference 1.25 V (analog part out of reset) takes about 1.7 seconds, and discharge to 0.75 V (analog part complete reset) takes about 1 second. My tests show that time frame, causing clicks, is actually longer than one second, thus actual reset threshold during powering down must be lower than 0.75 V.

The good thing in the circuit is that there's a system reset signal at the start of power up, which I can use to do something to this Vref input. I drew the following circuit:

enter image description here

and here the simulation zoomed:

enter image description here

Green is reset signal, blue is Vref output, and red is current through transistor's emitter.

I am looking for the feedback on this circuit, in particular:

  • is it correct in general, is there any better circuit?
  • what would be the best choice for transistor (I picked 2N2222 out of blue);
  • any advice on resistor values?
  • will the chosen values be ok for accelerated capacitor discharge not causing audible click/pop (the DAC output follows the Vref input very well)?

Edit (info for jonk): timing can be extended to the whole reset pulse width, e.g. 200-400 ms, and slope must not be sharp not to cause click/pop as DAC output follows the Vref voltage; I think small residue discharge voltage voltage (let's say, 0.4-0.7 V) would be acceptable, but must be confirmed through testing.

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  • \$\begingroup\$ Depending on how strong the reset signal is (i.e. how much current it can sink), you may be able to just put a diode between reset and vref such that when reset falls it pulls vref down with it. \$\endgroup\$ – td127 Oct 2 at 22:02
  • \$\begingroup\$ yeah, use a schottky diode. \$\endgroup\$ – Jasen Oct 2 at 22:06
  • \$\begingroup\$ Thanks. Important thing here: reset is digital, but Vref is analog, and the main task here is to ensure analog Vref is minimally affected by anything else. \$\endgroup\$ – Anonymous Oct 2 at 22:06
  • \$\begingroup\$ the diode will isolate vref from the digital reset signal when reset is high \$\endgroup\$ – Jasen Oct 2 at 22:07
  • \$\begingroup\$ that red curve looks wrong, are you sure it's emitter current? \$\endgroup\$ – Jasen Oct 2 at 22:08
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You could also use an nchannl mosfet like the 2N7002 off of the inverted reset which is fast and could also prevent noise from reaching the reference as the capacitive coupling between the gate an reference is small and high frequency (well above audio range)

enter image description here

Also, you might want to reduce the reference cap to 10uF (the UDA1334BTS needs at least 10uf) which would also reduce the startup time.

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The currents are low, the speed is slow, just use whichever transistor is most convenient.

common jelly-bean NPNs include 2n3904 and BC547 and SMT versions of them.

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Having an inverter in the circuit (your A1) is problematic because its behavior during power down in unpredictable.

A simple diode doesn’t have that problem. A standard diode will pull VREF down to about 0.7V, a schottky diode down to about 0.4V. R1 determines the rate of discharge.

When RESET_N is high (3.3V) D1 is off and completely isolated from VREF (2.1V).

I'm not convinced this will solve your audible pop problem (not an easy problem to solve), but at least this is a simpler circuit to implement your idea.

enter image description here

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