# How does electricty flow in a flip-flop circuit? I can't understand how memory bits work with NAND gates

Consider:

simulate this circuit – Schematic created using CircuitLab

The i bit is what we want to store, and the s bit is our setter bit. Each box is a NAND gate.

I am a little confused with how the flip-flop circuit works. Mainly, in what order things are happening.

Say we slowed time down to crawl, could the following happen:

1. Say s is 0 and i is 1.
2. 0 1 NAND -> 1. so a becomes 1
3. Now logic gate 3 runs
4. a is 1, but logic gate 4 hasn't run yet... so c is...0?

If c is 0, 1 NAND 0, o bit would become 1 :<

I am getting tripped up by ordering / speed of light here. Is it possible that the 4 gate, which computes c "did not have time to compute" itself, by the time the 3 gate runs? Is this question nonsense?

How does electricity flow here? Is there some order? If so, what determines this order physically?

I am a software engineer, studying logic gates for some fun. Please forgive me for what is probably a very noob EE question.

• I think part of the confusion here that I've not seen address in an answer yet is assuming c is 0/unknown start-up conditions. Memory circuits often have a reset built in to counter the often unpredictable conditions at startup, putting everything into a known state. – Dutchmanjonny Oct 5 at 9:31
• What happens if you "run" gates 2, 3 and 4 over and over a few times? Do you always get the same answer no matter what the first value of c was? (Note you are running the gates, the gates themselves don't run in an order, the "run order" is just a way for you to do the calculations) – user253751 Oct 5 at 9:38
• Some of the best explanations of logic gates I’ve found (I’m also from a CS perspective) is Ben Eater. He breaks things down, shows the details and explains very clearly. Strongly recommended! – Tim Oct 6 at 10:59
• In the Wikipedia article, it is a "gated D latch based on an SR NAND latch". – Peter Mortensen Oct 6 at 11:09

As a software guy, I had the same kinds of problems with HDL/Verilog... the hardware does not run in in any order, everything happens continuously, all at the same time. Your idea that "logic gate 4 hasn't run yet" doesn't quite match reality.

The real problem is that the digital design model is just a simplified approximation of reality, and what you're asking about is one of the corner cases where the model gives nonsense.

"How does electricity flow" --> the most accurate answer involves using Maxwell's equations to calculate the expressions for all parts of the electromagnetic field and flux throughout the entire system... but that requires complicated vector differential equation calculus, it's really too much for even a very simple circuit. The "lumped element" model is much easier to work with, because it makes some assumptions that there's no significant interaction between the elements except through the wires, so simpler DC circuits can be solved with Kirchoff's laws (KCL/KVL) and Ohm's law using algebra instead of calculus. Then there are even simpler models that treat electricity like water flowing through a pipe, or that treat electrons like tiny ping-pong balls on the outside of atoms; those models are easier to comprehend, but lead to a lot of misunderstandings and confusion.

"Digital logic" is an abstraction where we ignore the actual analog voltage and current in the signal, and only care about whether its voltage is within the "low" range or the "high" range. When a digital gate switches from low to high, the underlying analog signal has to pass through the voltages in between "low" and "high" -- here be dragons. Go through that zone too fast, and there will be unwanted radiated EMI, but go too slow, and there can be metastable values that break the illusion that the gates are digital.

Digital gates are an abstraction, the real underlying hardware is really analog. Real flip-flops have setup/hold timing requirements, because if the input changes during the clock edge, a race condition or metastable state can result in non-digital behavior that breaks the models.

I think there's an even simpler way to get what I think you're trying to ask: what if you take a digital inverter (a NOT gate) and connect its output to its input? If you imagine simulating it, the output seems like it should alternate between 0 and 1. But if you consider the analog voltage of the input and output, there may be a place in between "logic 0" and "logic 1" where the output and input are at the same voltage, so it would not alternate between 0 and 1, it would just be stuck at an invalid, non-digital logic value. It depends on what's actually inside the NOT gate.

In digital design, there is the idea of "propagation delay" which is how much time is required for a change in the "digital logic value" of the input to update the "digital logic value" of the output. Under the hood, some analog stuff is happening, involving mostly capacitance and available drive current. If you model the output section of the gate as a voltage-controlled current or voltage source which must charge up a small load capacitor connected to the output through some small output resistor, that gives an RC charge/discharge model of propagation delay. Reality is probably a lot more complicated, but it's a place to start. If you're an IC designer, you have to worry about all this stuff, but if you're just using an IC, you can often find propagation delay specifications in the datasheet. For example: 74HC08 As you can see, propagation delay depends on the power supply voltage (VCC) as well as the ambient temperature, and the load capacitance.

simulate this circuit – Schematic created using CircuitLab

Your idea that "logic gate 4 hasn't run yet" doesn't quite match reality, because logic gate 4 is continuously doing its job, regardless of whether its inputs have meaningful values or not. Garbage-in, garbage-out... However you can use the idea of propagation delay to observe that a change in input i requires one tpd "tick" to update a, two tpd "ticks" to update b and o, and three tpd "ticks" to update c. Meanwhile input s requires one tick to update b, two ticks to update c, three ticks to update o.

What you have with gates 3 and 4 is called cross-coupled NAND gates, and it forms a set-reset latch, one of the basic building blocks that flip-flops and memory elements are made of.

• Wow, what a fantastic answer Mark, thank you. I’ll play with integrating the concept of delays, and see where we can go. The simple idea that it all is analog underneath, and what that implies definitely opened my mind. If you have suggestions for books that a software eng would like to get even deeper on this stuff, would love suggestions! (Playing with simulating ram here: github.com/stopachka/ram/blob/main/src/ram.clj) – Stepan Parunashvili Oct 5 at 3:04
• Something that may help you design a simulator is that rather than thinking in terms of "levels" (1 or 0), consider "edges" (rising or falling). An edge arriving at a gate may cause its output to change, in the way that an event or interrupt may trigger a piece of software. – pjc50 Oct 5 at 8:59
• Fun fact: sometimes people actually use NOT gates, with analog feedback circuits, to make analog amplifiers. – user253751 Oct 5 at 9:36
• @user253751 Another fun fact, there are actually not gates specially made to be work better this way, look at the 4000UB (Unbuffered) series parts. – Dan Mills Oct 5 at 13:34
• @Rodney "Analog" Definition: "relating to or using signals or information represented by a continuously variable physical quantity such as spatial position, voltage, etc.". It has nothing to do with "analogous to something". – mbrig Oct 5 at 16:59

The circuit simulator applet has a bunch of sample circuits you can simulate, including well-known flip-flop types. It highlights logic levels on wires with color, producing a nice animation of how signals propagate though the schematic:

On the lowest level, the speed of signal propagation is often defined by parasitic resistances and capacitances: once the logic level changes, it takes some time for the current to flow before the location of charge carriers in the semiconductor die actually changes.

• Yes, but is the simulator applet actually a sufficiently accurate model in this case? For instance, would it capture meta stability? – Peter Mortensen Oct 6 at 11:03