I'm trying to understand the proper way to design a PCB to interface a Xilinx 7-series FPGA with a Marvell 88E1512 Ethernet PHY, without simply copying the design from an existing schematic.

The interface is a RGMII v2.0 with 3.3V LVCMOS as the IO standard, as stated in the Marvell datasheet. Not much is said in the Marvell datasheet about the impedance and termination requirements for the RGMII. As a matter of fact, it's not super clear what the output impedance is of a 3.3V LVCMOS driver from the FPGA either. I have gathered from some forum posts that it depends on the drive strength setting as well as the IBIS model. Unfortunately, I don't have access to any IBIS simulation modeling tools.

I can think of 2 scenarios for the FPGA output:

  1. The LVCMOS driver is very low impedance, so I should add a series resistance to conform to a specific characteristic impedance.
  2. The LVCMOS driver is already designed to implement a specific output impedance.

and I can think of 2 scenarios for the Marvell PHY:

  1. The termination is handled internal to the chip, so no external termination resistor is needed
  2. An external termination resistor is required.

The RMII routing guideslines from Cadence recommends a 50 ohm trace impedance, but no real rationale is given.

I have too many unknowns: Can someone give me some hints? What is the correct configuration, and how would I have extracted this from the datasheets?


2 Answers 2


I've been working on a Gigabit Ethernet project for months, and so far I checked datasheets from Realtek, TI, Microchip, and a few reference designs, here is what I've found out.

0. High-speed routing guidelines are sometimes ignored for RGMII, but big manufacturers recommend them.

In many low-cost products, the RGMII signals are routed with no regards of high-speed routing guidelines. In some boards, I've seen them routed as uncontrolled traces on a two-layer board, with no ground plane, no length matching, no termination resistor, etc. Apparently, even with a rise time of 750 ps, RGMII's 125 MHz operating frequency is still forgiving enough when your traces are sufficiently short. These boards seemed to work without problems. I've even seen 22 Ω series resistor and 20 pF grounded capacitors added to the RGMII clock lines as a hack for an extra delay to compensate for the timings on the unmatched traces.

On the other hand, major manufacturers like Texas Instruments or Microchip require the users to adhere to high-speed routing guidelines, because they want to avoid their clients to end up with a non-functional design.

  • 4-layer Board. Continuous Ground Plane.

  • Route RGMII as 50 Ω Transmission Lines

  • Minimize the use of vias, route all RGMII traces on one layer if you can. When vias must be used, add stitching capacitors or stitching vias.

  • Source Termination

  • Length-Matching All Traces - match all RX traces to each other, and match all TX traces to each other.

If you don't want to take any chance, it's recommended to follow them.

1. RGMII is terminated by source termination.

Like many point-to-point high-speed CMOS signals, RGMII is terminated by connecting a series resistor to the transmitter's output (which must be physically close). Then, the resistor is connected to its destination via a transmission line. The input side of the receiver is high-impedance, and has no termination. Any reflected energy is dissipated when it has traveled back to its source. This is known as source termination. See High-Speed Digital Design - A Handbook of Black Magic by Howard Johnson, Chapter 6, page 231 for details.

Source Termination Source: High-Speed Digital Design by Howard Johnson, fair use.

The value of the resistor is chosen, so when it's added to the output impedance of the driver, matches the characteristic impedance of the transmission line as a whole.

  • Zt + Zs = Z0.


  • Zt = External series Termination resistor,

  • Z0 = Characteristic Impedance of the transmission line, and

  • Zs = Output Impedance of the driver.

The characteristic impedance of the transmission line is arbitrary, usually for standardization, it's chosen to be 50 Ω microstrip.

As Howard Johnson pointed out, it's actually impossible to select an ideal series resistor here, since the output impedance of CMOS is not controlled, "not only is there a wide variation in impedance from the HIGH state to the LOW state, but there is an even wider variation from chip-to-chip, and between manufacturers of the same chip, and over the allowed operating temperature range, and over the allowed power-supply voltage range."

In practice, the output impedance of a CMOS chip is usually assumed to be around 10 Ω or 20 Ω. Thus, a 22 Ω, 27 Ω, or 33 Ω resistor is usually selected, and assumed to be "good enough". If the signal integrity is unsatisfactory, it can be fine-tuned by trial-and-error - replace it with another one, or even deleting it by using a 0 Ω resistor (thus, it's usually a good idea to leave a resistor component anyway, because you can always delete it later by a 0 Ω jumper).

It's generally recommended that the physical size of the resistor be less or equal to 0603 to minimized the impedance discontinuity.

For RGMII, it means the TXCLK, TXEN, TXD0, TDX1, TXD2, TXD3 should have a resistor close to the MAC, and RXCLK, RXDV, RXD0, RXD1, RXD2, RXD3 should have a resistor close to the PHY.

Source Termination Resistors Between PHY and MAC

Source: Microchip KSZ9893RNX Hardware Design Checklist, fair use.

Microchip says...

It is recommended to place series termination resistors on all RGMII output pins. Refer to Figure 8-3 for output pin placement. Combined with the output pin impedance, these series resistors provide the means to tune and match the PCB trace impedance to minimize ringing, and thus improve signal integrity and reduce EMI. The typical resistor value ranges from 22 Ω to 50 Ω with the optimum value being dependent on the board layout. A resistor value of 33 Ω can be used as the starting point for the schematic design.

2. The RGMII output is probably a standard, unmatched LVCMOS, unless there's evidence to the contrary.

It's self-evident: if the datasheet doesn't mention anything about the output impedance of the RGMII driver (or sometimes, only says it's LVCMOS output), then it is LVCMOS, and you need to introduce source termination resistors.

This can be confirmed by performing an exhaustive search for "RGMII" or "impedance". In most Ethernet PHY, MAC, or microcontroller datasheets, you won't find anything.

On the other hand, a matched output impedance of 50 Ω is usually highlighted in the datasheet. In this case, you can and should omit the termination resistor.

DP83867 Highlights DP83867 Impedance Control Source: Texas Instruments DP83867 Datasheet, fair use.

If you cannot find something like this, it's unmatched.

Many FPGAs allow an extremely flexible control on the output driver, including programmable termination, rise time, or output impedance. Consult the datasheet of your FPGA for more information.

It's also very possible that only the PHY or the MAC offers a matched output impedance, in this case, the outputs on the unmatched device still needs to be source-terminated on one end.

3. Use the PHY delay option for RGMII clock signals. If the RGMII traces are length-matched, it should work with the default 2 ns delay..

In the RGMII specification, for both directions, data and clock are simultaneously driven, but the clock is required to be delayed by 2 ns at the destination. This can be accomplished by manually adding a 2 ns delay line at RXCLK and TXCLK, but such a delay line requires a huge board space.

For modern PHYs, it's possible to add a 2 ns internal delay on both directions. Some MACs also support the option. I recommend to rely on the delay option at the PHY for both RX and TX, without introducing it at the MAC/FPGA to avoid the confusion on who's adding the delay.

Also, some PHYs allow one to fine-tune the RX/TX delay in a 0.25 ns step when the timing is problematic. But it's much easier to spend some time to match the RGMII traces at board level. Match all RX lines as an individual group, and match all TX lines as an individual group (you don't need to match both as a single group), thus avoiding the trouble of fine-tuning them altogether (which requires either a high-speed oscilloscope, logic analyzer, or trial-and-error using a loopback link).

  • \$\begingroup\$ Thanks for the detailed answer. I will go ahead and plan to have a series resistor footprint and do a bit of trail and error to see what works. I wish that IBIS modeling wasn't the only way to preplan this, but it is what it is. \$\endgroup\$ Oct 5, 2020 at 13:35

If the interface is described as "CMOS" then you should not expect the driver or receiver to be matched on-chip. If they were, then they wouldn't be "CMOS".

The RGMII interface runs at a nominal 250 Mb/s per lane, with a 125 MHz clock. If the rising and falling edges aren't driven too fast (while still respecting the maximum rise and fall time limits of the RGMII standard), you should not require terminations if the trace lengths are less than about 12 cm.

It is still a good idea to include series resistors at the drivers to be able to slow down the edges if needed. Without access to IBIS models, you may simply have to wait until you've built a prototype and then optimize the resistor values based on real-world measurements. For the first samples, 5 or 10 ohms is probably reasonable.

On the TXD lanes you will also have some ability to control the drive strength and edge speed of the FPGA IO blocks, from the constraints file.

The LVCMOS driver is very low impedance, so I should add a series resistance to conform to a specific characteristic impedance.

The CMOS driver is low-impedance compared to the trace. You want to add a series resistor to slow the edge speed, but you do not want to match the trace impedance (if you did that, you'd reduce your signal amplitude by 1/2, which is not how CMOS is designed to be used).

The LVCMOS driver is already designed to implement a specific output impedance.

It is not. Or, the output impedance is much lower than any practical trace impedance, and will vary from unit to unit due to manufacturing variation.

This is by design and expected. CMOS is not expected to be used with matched-impedance traces.

The RMII routing guideslines from Cadence recommends a 50 ohm trace impedance, but no real rationale is given.

I wouldn't take that too seriously. Possibly it is defined in the RMII spec (which I'm not familiar with). Using controlled-impedance traces is desirable in order to know that your length-matched traces are also delay-matched.

(Also, you are using RGMII, not RMII, so advice about RMII does not strictly apply to your application)

What is the correct configuration, and how would I have extracted this from the datasheets?

Basically, when it says the interface is CMOS, it is telling you that the drivers, receivers and traces are not impedance-matched.

You may have to look at application notes and user guides rather than datasheets. For example the Cadence document you linked to refers to a Renesas application note that gives some good recommendations.

Howard Johnson and Martin Graham's book, High Speed Digital Design: A Handbook of Black Magic is also an excellent reference for designs in this bandwidth range (and up to 1 or 2 Gb/s), and is one you'll see on many SI engineer's bookshelves, particularly if they've been in the business long enough to have worked at such "low" speeds.

  • 2
    \$\begingroup\$ The RGMII standard specifies a maximum rise time of 750 ps. \$\endgroup\$ Oct 5, 2020 at 2:12

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