I am designing a gate driver for SCT3160KL using a UCC21732 gate driver ic from Texas Instruments. I have made roughly made the circuit using the ic, but I want to test its overcurrent protection circuit. Would just a DC voltage in series with the mosfet work? I tried this on Pspice but it is not giving the right solution.

Apologies if this is a trivial question,I'm not nearly an expert in this field.

EDIT 1:- So thanks to csabahu's answer I did manage to make the circuit, and it does trip at the required current (i.e Drain current 17 A as per datasheet). But my supervisor says that there's a lot of phase lag between the OC pin voltage and the sense voltage. I don't get what he means entirely - "Design the RC filter to make the detection instantaeneous , i.e no lag". How do I do this? Here is the schematic & waveforms:- Waveform Schematic

(L5 is parasitic inductance) This shows the V_GS and FLT_N pin voltages

FLT_N and V_GS

Also, I am trying to simulate the double pulse test for this analysis. Is there anything wrong in the schematic? I selected D1 with current rating = Drain current rating of MOSFET (17 A). Is this wrong? schematic-2

  • \$\begingroup\$ You better add a dummy load in series, search for SMPS repair tricks. \$\endgroup\$ Commented Oct 5, 2020 at 7:36
  • \$\begingroup\$ You are using a fairly high switching frequency, there is still a large margin in the RC time constant. You can try to decrease until the peak begins to appear at the beginning of the waveform. With a smaller time constant, the phase difference also decreases. Look at the magnification of how wide the starting peak is for you and adjust the RC time constant accordingly. Probably 5x smaller will be enough (1k, 220pF). \$\endgroup\$
    – csabahu
    Commented Oct 12, 2020 at 14:47

1 Answer 1


Here you see how overcurrent protection works. In case of overcurrent, it switches off the IGBT and sends a /FAULT signal to the CPU. igbt1


All signals from power on to overcurrent fault: igbt3

  • \$\begingroup\$ thank you for your answer, can you tell me how I can simulate the fault at /FLT pin? \$\endgroup\$
    – SM32
    Commented Oct 7, 2020 at 6:47
  • \$\begingroup\$ I connected an ideal inductor to the Drain circuit. After that, I gave a control signal for a longer time to turn on. This resulted in a linear increase in IGBT current over time. The current had to reach the set limit (now low enough) before I turned it off. This will turn off by the overcurrent protection. The / FLT signal itself was generated by the control circuit, I had no influence (nor the ability) to create it. \$\endgroup\$
    – csabahu
    Commented Oct 7, 2020 at 7:06
  • \$\begingroup\$ My problem is that I know how I want it to work theoretically, but I'm unable to simulate it. I even followed your circuit just using SCT3160KL in place of IGBT, but my /FLT pin stays high at 5 V. Prior to this I'd checked my external gate resistances for turn-on times & used the same here. What am I doing wrong? \$\endgroup\$
    – SM32
    Commented Oct 7, 2020 at 7:18
  • \$\begingroup\$ Are you showing a schematic? The / FLT signal is generated when the voltage at OC exceeds 800mV. \$\endgroup\$
    – csabahu
    Commented Oct 7, 2020 at 7:24
  • \$\begingroup\$ Thank you I got it to work. Just a clarification - Rsense = Vsense_max/Isense_max right? So here I_max = Drain current, how do I get Vsense? I am confused if it should be the threshold Gate to Source voltage? \$\endgroup\$
    – SM32
    Commented Oct 9, 2020 at 8:01

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