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A SystemVerilog module using an always@ block with a gated trigger does not compile in Quartus Prime Lite (20.1). Quartus Prime reports the following compiler error message:

Error (10170): Verilog HDL syntax error near text: "iff"; expecting ")".

However, the "iff" conditional in the always@ sensitivities list is SystemVerilog-2005 compliant. The module does successfully compile and simulate using ModelSim-Intel Starter Edition.

The following is the SystemVerilog code:

module always_ff_process();

reg [7:0] sum,a,b;
reg       parity;
logic     clk = 0;
reg       rst = 0;

initial begin
  $monitor ("@%g clk = %b rst = %b a = %h b = %h sum = %h parity = %b", 
  $time, clk, rst, a, b, sum, parity);
  #1 rst = 1;
  #5 rst = 0;
  #2 a = 1;
  #2 b = 1;
  #2 a = 10;
  #2 $finish;
end

always #1 clk ++;

// use of iff makes sure that block does not get
// triggered due to posedge of clk when rst == 1
always_ff @(posedge clk iff rst == 0 or posedge rst)
begin
  if (rst) begin
    sum    <= 0;
    parity <= 0;
    $display ("Reset is asserted BLOCK 1");
  end else begin
    sum    <= b + a;
    parity <= ^(b + a);
  end
end

endmodule

I obtain no compiler error message using ModelSim-Intel and the following correct simulation results:

@0 clk = 0 rst = 0 a = xx b = xx sum = xx parity = x
Reset is asserted BLOCK 1
@1 clk = 1 rst = 1 a = xx b = xx sum = 00 parity = 0
@2 clk = 0 rst = 1 a = xx b = xx sum = 00 parity = 0
@3 clk = 1 rst = 1 a = xx b = xx sum = 00 parity = 0
@4 clk = 0 rst = 1 a = xx b = xx sum = 00 parity = 0
@5 clk = 1 rst = 1 a = xx b = xx sum = 00 parity = 0
@6 clk = 0 rst = 0 a = xx b = xx sum = 00 parity = 0
@7 clk = 1 rst = 0 a = xx b = xx sum = xx parity = x
@8 clk = 0 rst = 0 a = 01 b = xx sum = xx parity = x
@9 clk = 1 rst = 0 a = 01 b = xx sum = xx parity = x
@10 clk = 0 rst = 0 a = 01 b = 01 sum = xx parity = x
@11 clk = 1 rst = 0 a = 01 b = 01 sum = 02 parity = 1
@12 clk = 0 rst = 0 a = 0a b = 01 sum = 02 parity = 1
@13 clk = 1 rst = 0 a = 0a b = 01 sum = 0b parity = 1

Both Quartus Prime Lite and ModelSim-Intel Starter Edition support SystemVerilog-2005. However, Quartus Prime Lite's compiler doesn't appear to support clock-edge gating (the "iff" conditional) even though it's legal SystemVerilog-2005. I have set the settings of both compilers to SystemVerilog and I cannot find any other applicable settings.

Please advise. Thank you!

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  • \$\begingroup\$ Is it possible you're running into this? insights.sigasi.com/opinion/jan/vhdls-crown-jewel/… \$\endgroup\$ – user_1818839 Oct 6 '20 at 10:23
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    \$\begingroup\$ I suspect it's not supported as synthesizable (Quartus Prime), but is supported by the simulator (ModelSim). It's an odd way to implement clock gating, so perhaps it just hasn't been implemented. You'd be surprised how different the simulators can be - they are immensely complicated pieces of software. \$\endgroup\$ – awjlogan Oct 8 '20 at 15:36
  • \$\begingroup\$ @awjlogan thank you for your response. I also suspect that "iff" clock-gating of the always@ block isn't implemented in Quartus Prime Lite. I will choose a different implementation then. \$\endgroup\$ – HypeInst Oct 8 '20 at 22:07
  • \$\begingroup\$ For which FPGA model are you writing this code? \$\endgroup\$ – Arseniy Oct 9 '20 at 5:40
  • \$\begingroup\$ @Arseniy it's for the Cyclone V. \$\endgroup\$ – HypeInst Oct 9 '20 at 18:13

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