Hello and thanks beforehand. I have this document in altium that has some weird issue with some vias. As you can see in this photo, some vias are like greyed out on the grey part, and they are not affected by the clearance rules between the vias and the polygon pours. However, i cannot think what is the problem with those vias since the properties between those vias and the correct ones (line the one on the bottom left corner) are exactly the same. By replacing those vias with a copy of a normal one everything goes back to normal but there are a lot of them and i would rather know what causes this. DRC does not throw any errors which is what bugs me the most. It only happens in one layer for each via, so if one via is greyed out in one layer it won't be for the rest of the layers.
This are the properties of a normal via
And this are the properties of a greyed out via.