I came across the Isola IsoStack website that lets me test PCB stack-up using Isola substrates:
My project is using a stripline design with a 1oz copper inner layer and trace width of 0.010". The tool calculated impedance at 50 ohms for my stackup but it complains that it violates an IPC-2141A constraint where trace height over trace width must be less than or equal to 0.11. The tool used 0.00125" for 1 oz copper height and my width of 0.010" to get a ratio of 0.125.
Can someone give me an overview on how this ratio applies to trace/signal behavior? If my signal is only DC-50Mhz, does it still apply or can be ignored? I tried to search for IPC-2141A and any term matching height/width ratio and most results talk more about current capacity or, oddly, hole aspect ratios.