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enter image description here

The above image is regarding the Miller Capacitance present in the MOSFET.

I am finding it tough to understand the concept of Miller capacitance. I am trying and researching documents and videos to understand it.

I am not able to understand the graph.

Question 1: Assume Vdc (as per the image) is 20V. And VG is applied from 0V to 5V.

From the graph, at the initial part, when VG slowly ramps up, Voltage at VDC also increases? How is it possible? I think I am failing to understand the basics of capacitors and capacitance which is why this query arises. Can someone help me to clarify this doubt and help me understand a little more intuitive on this capacitor action during millers effect?

Question 2: Why does the Plateau occur? Can someone help me with the concept of miller plateau?

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  • \$\begingroup\$ Do you fully understand the plot when there is no Miller effect, so \$C_{gd}\$ = 0 ? Then do you understand the effect of the Miller capacitor ( \$C_{CB}\$) in the common emitter circuit? Yes that's a different circuit but there it is easier to understand the Miller effect. Including the picture with all those added scribbles is confusing. I think this plot is confusing as it appears to plot voltages over time but it doesn't say "time" on the X-axis. \$\endgroup\$ Oct 7, 2020 at 12:56
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    \$\begingroup\$ Can't you find a better quality picture with all that scribbled stuff removed? The miller capacitance causes negative feedback to the gate and thus, for a short period, you get the plateau. \$\endgroup\$
    – Andy aka
    Oct 7, 2020 at 12:58
  • \$\begingroup\$ I have added a better quality picture. \$\endgroup\$
    – user220456
    Oct 7, 2020 at 13:00
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    \$\begingroup\$ Have you studied negative feedback? Do you know how an inverting op-amp works and how it produces a virtual ground at the inverting input terminal? If no and no then this question is likely a step too far for you. \$\endgroup\$
    – Andy aka
    Oct 7, 2020 at 13:23
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    \$\begingroup\$ Vdc is fixed, it's the supply voltage. Vd is what changes as the MOSFET conducts. \$\endgroup\$
    – Finbarr
    Oct 7, 2020 at 13:37

2 Answers 2

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Take an opamp with gain of 100,000.

Install a 100pF capacitor from VIn- to the output.

Ground the Vin+

Now apply 1 microvolt sinusoid at Vin-.

The voltage source will have to charge up that 100pF capacitor. The other end of the capacitor will be changing, by 100,000X more voltage.

Since the required charge on a capacitor is Q = C * V, here we have a huge problem, because the effective input capacitor is

  • (1 + 100,000) larger than what we expected.

This ratio (1 + voltage_gain) is the Miller Multiplication of the actual capacitor.

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  • \$\begingroup\$ 1) include a circuit drawing 2) this is a correct explanation of what the Miller effect is, however it doesn't tell us how and why that relates to the circuit shown in the question. \$\endgroup\$ Oct 7, 2020 at 13:03
  • \$\begingroup\$ Thank you for the answer. But, I just want some kind of intuitive or simple explanation regarding the miller effect in MOSFETs. Because, I have searched many articles and pages to get proper understanding. But all show the math or use some sort of explanation which is not understood by me. Kindly request to explain in simple terms with respect to the basics of capacitors \$\endgroup\$
    – user220456
    Oct 7, 2020 at 13:05
  • \$\begingroup\$ Mosfet, vacuum tube or opamp : doesn't matter. This answer IS the simple explanation. It chose an opamp because the crazy high gain makes the plateau flatter explaining it better. \$\endgroup\$
    – user16324
    Oct 7, 2020 at 15:36
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Well, the situation is quite complicated and I assumed pure resistive load.

enter image description here

For \$V_{IN} = 0V\$ we have \$V_{C_{DG}} = 12V\$ and \$V_{C_{GS}} = 0V\$

But at the very first moment when \$V_{IN}\$ "jumps" to \$5V\$. The voltage at the gate will immediately start to rise toward \$5V\$. As \$C_{GS}\$ begins to charge.

But this rise in gate voltage will start to influence the \$C_{DG}\$ capacitor also. And because the voltage across the capacitor cannot changes instantly. This will slightly increase the voltage at the drain beyond the \$V_{DD}\$ value. And the \$C_{DG}\$ capacitor begins the discharge phase and the discharging current starts to flow.

As I was trying to show here:

enter image description here

And the MOSFET is OFF because \$V_{GS}\$ is well below the MOSFET threshold voltage.

As \$C_{GS}\$ capacitors continue to charge towards \$V_{IN} = 5V\$ the capacitor voltage will reach the MOSFET threshold voltage. This will open the MOSFET and \$I_D\$ current begins to flow. This causes the voltage at the drain, measured relative to the ground will start to decrease. The \$C_{DG}\$ capacitor will now start the discharge into the MOSFET. But to change the voltage at the drain and across \$C_{DG}\$ capacitor current is needed (\$I = C\cdot \frac{\Delta V}{\Delta t} \$) Capacitor current is proportional to the rate of voltage change across it (proportional to how quickly the voltage across the capacitor is changing). Thus, because the voltage at the drain needs to change from \$V_{DD}\$ to \$0V\$. Thus, the \$C_{DG}\$ capacitor needs current for this to happen. And all this current must be provided by an input signal source. And because of a fact that \$\frac{\Delta V}{\Delta t}\$ across \$C_{DG}\$ is much larger than \$\frac{\Delta V}{\Delta t}\$ across \$C_{GS}\$. Almost all the input source current will flow into the \$C_{DG}\$ capacitor. Thus the $\V_{GS}$ will rice very very slowly (Plateau effect).

After sometime when \$C_{DG}\$ discharges process is completed (\$V_{C_{DG}} = 0V\$ ) and the drain voltage reaches \$0V\$. The \$C_{DG}\$ will start a charging phase in the opposite direction. But now the \$\frac{\Delta V}{\Delta t}\$ is small because the drain voltage is at 0V and only the gate voltage now needs to reach the final value \$V_{IN}\$ value. enter image description here

enter image description here

And in the real world, this process will look like this:

enter image description here

In yellow the voltage at the gate (\$V_{IN} = 5V\$) and in "light blue" the voltage at the drain \$V_{DD} = 12V\$.

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  • \$\begingroup\$ Truly a Wonderful explanation. This is the type of detail that I was expecting. Thank you very much. Just have a few questions. When the MOSFET started to conduct and the instant drain current starts to increase, since the voltage across the gate drain capacitance cannot change instantaneously, the current from the signal source goes to the capacitor and clamps the voltage at the value and thereby maintaining voltage across the capacitor. Is my understanding correct? And last question - Could you please also state how negative feedback is achieved in simple terms as you just did \$\endgroup\$
    – user220456
    Oct 7, 2020 at 17:42
  • \$\begingroup\$ Re reading your answer again . I didn't understand when you said - to bring to voltage from Vdd to 0V, it needs capacitor current. But why does it need capacitor current to do this? \$\endgroup\$
    – user220456
    Oct 7, 2020 at 17:55
  • \$\begingroup\$ But this is a parasitic capacitance build into the MOSFET. And when to MOSFET is OFF we have one end of a capacitor connected to Vdd and the second one (the left plate) to the gate 0V. So, the Cdg capacitor is charged. When the MOSFET started to conduct and the drain current starts to flow. And the voltage at the drain (one leg of a Cdg capacitor) also "wants" to change due to the voltage drop across load resistance. But you cannot change the voltage across the capacitor without the current. And the only path for this current is via an input voltage source. \$\endgroup\$
    – G36
    Oct 7, 2020 at 19:01
  • \$\begingroup\$ Thank you. Could you please confirm my doubts asked in my first comment please \$\endgroup\$
    – user220456
    Oct 7, 2020 at 19:08
  • \$\begingroup\$ Notice that when the MOSFET starts to turn-ON the I_Cdg current starts to flow because the voltage at the drain starts to decrease. But the rate of change is limited by Cdg and input source current Is = I_Cgs + I_Cdg . Why? Because, if the rate of change of a drain voltage is too high all the gate current needs to flow into the Cdg capacitor, so there is no current left for the Cgs capacitor (the input current is limited to Vin/Rg = constant ). \$\endgroup\$
    – G36
    Oct 7, 2020 at 20:27

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