What is full scale of flash ADC?

Question

My input signal is a sine of amplitude 1 so the input ranges from -1 to 1 so the range is 2 (pk-pk.)

On the other hand, the flash voltage divider ladder goes from 0 to Vref.

Which one of the two options is considered full scale for SQNR?

In the SQNR formula shown below we see they take a range and divide it by 2, so it may say that we take peak to peak value of the input and divide it by 2 (to get the amplitude ) of the signal.

Why can't the flash ladder voltage range be considered as full scale voltage?

Answer 1

SQRN is an |absolute value| (positive only) for AC signals and thus the reference is to zero and not negative peak or peak to peak.

• if you do not amplify your input signal to full scale equal 0 to Vref, then your SQRN value for V, remains at 1V peak. However if you do then your new Vmax= Vref/2

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Answer 2

Your problem is that you are mixing up the ideal goal with the imperfect and economically manufacturable tools available to work towards it.

Your signal is AC, but your ADC can only measure positive voltages.

Thus in order to use the ADC, you must inject a DC offset.

However, your formula applies only to an AC signal, so before you can use it on the data output from the ADC, you must remove that offset.

This isn't always quite as easy as it sounds. In practical systems there are typically other things you need to take care of on the way into and out of the ADC as well.

But in simple terms, you are adding a DC offset in the circuit so you must remove it again in the math.

If your circuit can optimally map the input range of -1 to +1 volts to an ADC range of 0 to Vref, then your full scale reading would be Vref/2. If you map it in some other way, for example to Vref/2-1v to Vref/2+1v then your full scale range is the maximum amplitude representable in that mapping. But if you consider the actual input range, then you also have to consider what an LSB maps back to in terms of a step in input voltage...

Typically people try to make the input circuit optimally map to the ADC, and thus just consider the ADC itself, which is where you get rules of thumb such as about 6 dB per bit. But if your circuit can't actually use the full range of the ADC, then you'd get less...