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I am working on a circuit that contains CD4043 R/S latch. The design on the breadboard works and everything is great, as soon as the PCB was manufactured and components were soldered, an issue with the latch arose.

Cirucit diagram

I use the switch-button on the SET input to initialize the latch and for the restart. But somehow on the output, I always get 0 with no matter what is on RESET input. The exception is when the button is actually pressed, then I have 5V.

However, as I said before, there were no problems on the breadboard.

What I did, but it doesn't help:

  1. All the unused latch inputs connected to the ground.
  2. Decoupling capacitors across VCC and ground.
  3. The design itself based on logic components. Calculated delay times, there should be still enough time for the latch to recognize 5V from the switch, but it somehow doesn't 'hold' it.
  4. First used SPDT switch, then replaced it with single pole switch + resistor, to avoid open circuit state at the moment of switch.

Nothing has helped :'( :'( :'(

Please advice. If you need extra details I am ready to provide.

EDIT 1: I attached the actual electrical circuit to make it clear. Circuit with single pole switch mentioned in 4.

EDIT 2: I need the latch output to depend not only on the input signals (A and B in U3), but also on its own output, i.e. if at least one of the input signals is off, the latch goes to 0. As soon as input signals are back, the latch should stay in 0 state until it's initialized with the switch S1.

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    \$\begingroup\$ Are you sure that's really the circuit you've built? There are a few things wrong with it (such as the switch shorting out the supply and the transistor sorting the output of the 1st gate to ground. \$\endgroup\$
    – brhans
    Commented Oct 8, 2020 at 3:02
  • \$\begingroup\$ I inserted a picture. The transistor is used as a switch. As well as a switch - to initialize the latch and reset the SET input if I can say so. \$\endgroup\$
    – IvetaS
    Commented Oct 8, 2020 at 14:17
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    \$\begingroup\$ Ok - the addition of all those resistors which are not present in your original sketch make a big difference. \$\endgroup\$
    – brhans
    Commented Oct 8, 2020 at 14:44
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    \$\begingroup\$ Better , but NEVER leave CMOS inputs floating and missing decoupling cap (>=0.01uF) WHy because when logic gate switches it discharges xx pF on Vdd to Vss per gate and then Vdd can get noisy \$\endgroup\$ Commented Oct 8, 2020 at 20:14
  • \$\begingroup\$ Missing connection from Transistor Out and S1 needs a cap across switch for POR \$\endgroup\$ Commented Oct 8, 2020 at 20:20

1 Answer 1

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This is an odd way to do what you are trying with feedback to edge trigger to use a CD4000 series latch (old tech) then using an NPN to shunt the input NAND gate.

A better question might show the timing diagram you want to design or a truth table or a State Diagram. You just want a Power on Reset (POR) with a 2-OR input=0 Latch from 1 to 0. There are many ways to do this without a transistor shorting the output even though the old CD4000 series is only 300 Ohms to 1k output Z while 74HC is ~ 50 Ohms.

  • My guess is you overlooked that both latch and FF outputs are high when both inputs are On.
  • Or you changed the 3 input NAND logic family to 74HCxx and the NPN base R is too high and perhaps 470R might do the trick. Check Vce.

If inductive circuit delay of some xx ns made your breadboard work try adding an xxx pF cap to the transistor to suppress crosstalk.

enter image description here

enter image description here


Better Way. Although POR stays low is better than Power On Set.

schematic

simulate this circuit – Schematic created using CircuitLab

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    \$\begingroup\$ Thank you for your comment. \$\endgroup\$
    – IvetaS
    Commented Oct 8, 2020 at 14:20
  • \$\begingroup\$ I need my latch to depend not only on the input signals but also on its own output. I.e. if one of the input signals off and then immediately back, I want the latch to stay on its 0 state. \$\endgroup\$
    – IvetaS
    Commented Oct 8, 2020 at 14:28
  • \$\begingroup\$ I might not understand what you mean under your bullets. But all the inputs and outputs are measured several times. Everything looks fine on RESET input. And do you mean that using the CD4000 family which is old tech influences the circuit functionality? And as I mentioned before the circuit works on the breadboard, but not on the PCB \$\endgroup\$
    – IvetaS
    Commented Oct 8, 2020 at 15:09
  • \$\begingroup\$ When both SR are high, both outputs are high, what latency effects during race condition going off? All you need is a POR and an edge triggered Clock FF not a latch with loopback \$\endgroup\$ Commented Oct 8, 2020 at 16:49
  • \$\begingroup\$ The breadboard is different why, Impedance and inductance delays, stray crosstalk? \$\endgroup\$ Commented Oct 8, 2020 at 16:55

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