CD4043 latch breadboard VS PCB

Question

I am working on a circuit that contains CD4043 R/S latch. The design on the breadboard works and everything is great, as soon as the PCB was manufactured and components were soldered, an issue with the latch arose.

I use the switch-button on the SET input to initialize the latch and for the restart. But somehow on the output, I always get 0 with no matter what is on RESET input. The exception is when the button is actually pressed, then I have 5V.

However, as I said before, there were no problems on the breadboard.

What I did, but it doesn't help:

1. All the unused latch inputs connected to the ground.
2. Decoupling capacitors across VCC and ground.
3. The design itself based on logic components. Calculated delay times, there should be still enough time for the latch to recognize 5V from the switch, but it somehow doesn't 'hold' it.
4. First used SPDT switch, then replaced it with single pole switch + resistor, to avoid open circuit state at the moment of switch.

Nothing has helped :'( :'( :'(

Please advice. If you need extra details I am ready to provide.

EDIT 1: I attached the actual electrical circuit to make it clear.

EDIT 2: I need the latch output to depend not only on the input signals (A and B in U3), but also on its own output, i.e. if at least one of the input signals is off, the latch goes to 0. As soon as input signals are back, the latch should stay in 0 state until it's initialized with the switch S1.

Answer 1

This is an odd way to do what you are trying with feedback to edge trigger to use a CD4000 series latch (old tech) then using an NPN to shunt the input NAND gate.

A better question might show the timing diagram you want to design or a truth table or a State Diagram. You just want a Power on Reset (POR) with a 2-OR input=0 Latch from 1 to 0. There are many ways to do this without a transistor shorting the output even though the old CD4000 series is only 300 Ohms to 1k output Z while 74HC is ~ 50 Ohms.

• My guess is you overlooked that both latch and FF outputs are high when both inputs are On.
• Or you changed the 3 input NAND logic family to 74HCxx and the NPN base R is too high and perhaps 470R might do the trick. Check Vce.

If inductive circuit delay of some xx ns made your breadboard work try adding an xxx pF cap to the transistor to suppress crosstalk.

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Better Way. Although POR stays low is better than Power On Set.

^{simulate this circuit – Schematic created using CircuitLab}