Here's an example schematic:
Suppose top MOSFET is off, bottom MOSFET is on.
Driver turns bottom MOSFET off, by outputting 0V to its gate. Then driver turns top MOSFET on. This creates high dv/dt as the SW node swings from GND to +12V.
This injects current into the bottom FET gate via its Cgd Miller cap.
If the bottom FET gate is connected to the driver via a too high resistor, or a long inductive trace, or its internal gate impedance is too high, or whatever reason that causes its gate to not be held firmly enough below its threshold voltage, its gate voltage will rise, and it will turn back on. At this point both FETs are on and short the supply, which is a bad idea.
Question 1: How does High dV/dt affect this? Does it mean when the Input VBAT goes from 0V to 12V very quickly, the transistor will turn ON?
Yes, this would also pump current via the Miller cap into the base.
Question 2: How does adding a capacitor between base and emitter help to reduce this effect?
It creates a low impedance short at HF across the B-E junction which diverts the current going through the Miller cap and prevents it from going into the base and turning the transistor on.
Why can't it be added between VBAT and ground? Won't a capacitor added between VBAT and ground also reduce the dV/dt?
Yes, a cap between Vbat and GND would reduce dv/dt. But this is about cases where you can't do that, for example in the MOSFET driver above, you want to switch fast to minimize switching losses, which means high dv/dt at the switching node. If you put a cap to ground there it will be charged and discharged at each cycle, which means losses.
I have gone through and found that similar to a resistor voltage divider, 2 capacitors in series also acts as a capacitor voltage divider? Can someone please explain how?
Two impedances in series act as a divider, it works the same no matter what kind of impedance.
Question 3 : Is this a common emitter circuit as the emitter is common to both input and output?
Yes, it's a common emitter.
I just modeled the bottom transistor in the FET driver schematic above, and used a BJT instead to show the effect isn't limited to FETs. V1 is a square wave with high dv/dt that models the upper transistor switching. Here the base resistance is pretty low, so on the plot we see the transistor's Ic and Ib which correspond to current flowing through the internal Miller cap Cbc and then to ground via R1 and the B-E junction. Even if the transistor is off and B-E junction is not acting as a diode, it still has capacitance. I've put red arrows for the direction of current when collector voltage rises.
These base and collector currents exist even if the transistor is off, since they go through the internal capacitance. Vb plot shows base voltage, which also spikes due to voltage drop across R1.
Now increasing R1 to 10k...
The same current flows inside the transistor through the Miller cap Cbc as before, but due to R1's much higher value the voltage drop across R1 is now high enough to turn on the transistor. Thus the base current actually decreases compared to previous plot, because the base current no longer flows through the transistor pin labeled "base". Instead it flows through Cbc, then internally through the junction, turning the transistor on. Ic plot thus shows substantial collector current.
Now for the fun part:
Collector voltage starts to rise at point labeled "1". At this point the transistor is off and Vb rises as current through Cbc charges Base-Emitter capacitance and also leaks through R1. At point 2 Vbe is enough to turn on the transistor, thus Vbe junction turns on and takes most of the Cbc current. So, Vbe rises much more slowly, as a diode log V-I characteristic.
But the fun part is, at point 3 when collector voltage stops rising and thus stops pushing current through Cbc, the transistor doesn't turn off immediately. This is because the base-emitter capacitance contains charge that will have to be discharged through the B-E junction and through R1. This is why the turn-off is pretty slow.