# High dV/dt turning on BJT switching Circuit due to Miller capacitance

I have this BJT Switch circuit. Ccbo- collector base capacitance , Cleak- PCB layout parasitic capacitance.

In a design recommendation, I have a point which states - "Verify that the switch does not momentarily activate when its input supply is enabled. A common cause of this is miller capacitors (gate-drain / base-collector) in the switch to limit slew rate / current surge. Any capacitors to limit slew rate should be gate-source / base-emitter capacitors"

It is recommending to add capacitor between base and emitter.

My questions

Question 1: How does High dV/dt affect this? Does it mean when the Input VBAT goes from 0V to 12V very quickly, the transistor will turn ON? How will the transistor turn ON - because you need both transistor base-emitter voltage (assume to be more than 0.6V in this case) and base current to flow into Q2 for the transistor to turn ON? And how does it happen during dV/dt?

Question 2: How does adding a capacitor between base and emitter help to reduce this effect? I agree that the capacitor will reduce the dV/dt but why should it be added between Base-emitter of Q2? Why can't it be added between VBAT and ground? Won't a capacitor added between VBAT and ground also reduce the dV/dt?

I have gone through and found that similar to a resistor voltage divider, 2 capacitors in series also acts as a capacitor voltage divider? Can someone please explain how?

Question 3 : Is this a common emitter circuit as the emitter is common to both input and output?

Just want to understand in simple basic terms on what high dV/dt will do in the below case and how the high dV/dt effect is bad and how it is mitigated by adding a capacitor across base-emitter of a transistor? If the value of the capacitor can be calculated, how is it done?

• Why can't it be added between VBAT and ground? Think, what is already between VBAT and ground? Is the voltage between VBAT and ground constant or not? How would you measure VBAT? You ask a lot but from your questions it is evident that you have to take a step back and consider how things work. Take small steps from the things you do understand. Is this a common emitter circuit... You should already be able to answer this without question (know it) when you see above circuit for the first time. Oct 8 '20 at 7:47
• Yes sorry. Could you please provide an answer to my questions Oct 8 '20 at 7:49
• No, it would require a one-hour lecture. Maybe even two hours. Oct 8 '20 at 7:49

Q1: The high dV/dt causes a momentary current to flow through Ccbo+Cleak. This develops a voltage across R57 and turns on Q2.

Where Iturnon = (Ccbo+Cleak).dV/dt

Q2: Yes the added capacitor as suggested does indeed act as a voltage divider.

It acts in the same way as a resistive divider where the result is R1/(R1+R2). For the capacitive divider the result is Zc1/(Zc1+Zc2)

Adding a cap between VBAT and GND will suppress the dV/dt of the supply voltage to some extent but depends on the source resistance.

Reducing the value of R57 will also help as it will reduce the value of the parasitic turn on voltage. This may be a simpler answer.

Q3: Yes it is a common emitter circuit for the reason you state.

• Thank you very much for the clear answer. Could you please provide a path of the current flow which makes the transistor turn ON? How does the current flow and how does it reach the ground? Oct 8 '20 at 9:13
• For conventional current flow the parasitic current flows from VBAT through R52 and Ccbo+Cleak into GND. If the voltage developed across R52 exceeds ~0.6V then the base emitter junction will start conducting and turn the transistor on. In this case part of the current now flows as Ib. Oct 8 '20 at 9:25
• Thank you. So the parasitic current path flow which turns on the transistor is VBAT -> R57 (R52 from your comment) -> Ccbo + Cleak -> R403 -> GND. It is this current flow which helps to develop the base emitter voltage of -0.6V and turn on the transistor. Am I correct? But in this case, there would be no current flowing into the base right? So, how does the transistor turn ON? Oct 8 '20 at 9:36
• Yes, I forgot R403 in my answer. No current will flow through the base provided that Vbe remains below ~0.6V. As the turn on voltage of Q2 is reached part of Ileak flows into the base and turns on the transistor. Oct 8 '20 at 9:44
• Since, it is a PNP transistor, the base current should flow from the Emitter of Q2 (Pin 4) to Base of Q2 (Pin 5) and then through Ccbo + Cleak -> R403 -> GND, right? Oct 8 '20 at 9:51

Here's an example schematic: Suppose top MOSFET is off, bottom MOSFET is on.

Driver turns bottom MOSFET off, by outputting 0V to its gate. Then driver turns top MOSFET on. This creates high dv/dt as the SW node swings from GND to +12V.

This injects current into the bottom FET gate via its Cgd Miller cap.

If the bottom FET gate is connected to the driver via a too high resistor, or a long inductive trace, or its internal gate impedance is too high, or whatever reason that causes its gate to not be held firmly enough below its threshold voltage, its gate voltage will rise, and it will turn back on. At this point both FETs are on and short the supply, which is a bad idea.

Question 1: How does High dV/dt affect this? Does it mean when the Input VBAT goes from 0V to 12V very quickly, the transistor will turn ON?

Yes, this would also pump current via the Miller cap into the base.

Question 2: How does adding a capacitor between base and emitter help to reduce this effect?

It creates a low impedance short at HF across the B-E junction which diverts the current going through the Miller cap and prevents it from going into the base and turning the transistor on.

Why can't it be added between VBAT and ground? Won't a capacitor added between VBAT and ground also reduce the dV/dt?

Yes, a cap between Vbat and GND would reduce dv/dt. But this is about cases where you can't do that, for example in the MOSFET driver above, you want to switch fast to minimize switching losses, which means high dv/dt at the switching node. If you put a cap to ground there it will be charged and discharged at each cycle, which means losses.

I have gone through and found that similar to a resistor voltage divider, 2 capacitors in series also acts as a capacitor voltage divider? Can someone please explain how?

Two impedances in series act as a divider, it works the same no matter what kind of impedance.

Question 3 : Is this a common emitter circuit as the emitter is common to both input and output?

Yes, it's a common emitter.

Example: I just modeled the bottom transistor in the FET driver schematic above, and used a BJT instead to show the effect isn't limited to FETs. V1 is a square wave with high dv/dt that models the upper transistor switching. Here the base resistance is pretty low, so on the plot we see the transistor's Ic and Ib which correspond to current flowing through the internal Miller cap Cbc and then to ground via R1 and the B-E junction. Even if the transistor is off and B-E junction is not acting as a diode, it still has capacitance. I've put red arrows for the direction of current when collector voltage rises.

These base and collector currents exist even if the transistor is off, since they go through the internal capacitance. Vb plot shows base voltage, which also spikes due to voltage drop across R1.

Now increasing R1 to 10k... The same current flows inside the transistor through the Miller cap Cbc as before, but due to R1's much higher value the voltage drop across R1 is now high enough to turn on the transistor. Thus the base current actually decreases compared to previous plot, because the base current no longer flows through the transistor pin labeled "base". Instead it flows through Cbc, then internally through the junction, turning the transistor on. Ic plot thus shows substantial collector current.

Now for the fun part: Collector voltage starts to rise at point labeled "1". At this point the transistor is off and Vb rises as current through Cbc charges Base-Emitter capacitance and also leaks through R1. At point 2 Vbe is enough to turn on the transistor, thus Vbe junction turns on and takes most of the Cbc current. So, Vbe rises much more slowly, as a diode log V-I characteristic.

But the fun part is, at point 3 when collector voltage stops rising and thus stops pushing current through Cbc, the transistor doesn't turn off immediately. This is because the base-emitter capacitance contains charge that will have to be discharged through the B-E junction and through R1. This is why the turn-off is pretty slow.

• Yes, a cap between Vbat and GND would reduce dv/dt. I call a cap between Vbat and GND a supply decoupling capacitor. A supply decoupling capacitor is not going to influence dV/dt on an internal node much. Oct 8 '20 at 8:02
• @bobflux, thank you very much for the detailed and patient answer. Much appreciation your help. Just a question - Could you just draw the current flow path for your answers to my questions 1 & 2, please? Oct 8 '20 at 8:46
• And I have some confusion understanding this line - "If the bottom FET gate is connected to the driver via a too high resistor, or a long inductive trace, or its internal gate impedance is too high, or whatever reason that causes its gate to not be held firmly enough below its threshold voltage, its gate voltage will rise, and it will turn back on. At this point both FETs are on and short the supply, which is a bad idea." - Are you saying that the gate impedance should be high to avoid this MOSFET turn ON or the gate impedance should be LOW? Oct 8 '20 at 8:47
• Final question - When you say - "It creates a low impedance short at HF across the B-E junction which diverts the current going through the Miller cap and prevents it from going into the base and turning the transistor on." - Transistor also required Vbe voltage of around 0.6V to 0.7V for the transistor to turn ON including the base current, right? How does the transistor turn ON without the 0.7V? If it gets the required 0.7V, how and from where it is getting? Oct 8 '20 at 8:53
• Sorry for the 3 questions. Just trying to get to the bottom of the answer and understand it clearly and intuitively. Oct 8 '20 at 8:54