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I'm starting to use SVAs for formal verification. I run QuestaSim2019 and I can successfully import uvm_pkg (is it needed to use assertions anyways?): as I do import uvm_pkg::*; I get # -- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-it).

Following this guide I wrote my assertion:

property p_prop_name;
     @(posedge clk) disable iff (!sig1 && sig2) |-> sig3;
   endproperty

   a_assertion_name: assert property(p_prop_name);

As I tri to compile using vlog I get the following error:

** Error: (vlog-13069) sva/compx_sva.sv(34): near "|->": syntax error, unexpected |-> .

I checked the syntax and to me it looks alright. Any ideas why this should not work?

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    \$\begingroup\$ I’m voting to close this question because it's just a programming syntax error. would have been bettor for stackoverflow, but even tthere it's close to being a typo. \$\endgroup\$ – dave_59 Oct 8 '20 at 18:25
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Ok I solved it. The problem lies in the (wrong) usage of disable iff. As written here:

disable iff disables the property if the expression it is checking is active. This is normally used for reset checking and if reset is active, then property is disabled.

So it needs a boolean expression to evaluate. In my case, I just removed it and it is now working.

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