I'm starting to use SVAs for formal verification.
I run QuestaSim2019 and I can successfully import uvm_pkg (is it needed to use assertions anyways?):
as I do
import uvm_pkg::*; I get
# -- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-it).
Following this guide I wrote my assertion:
property p_prop_name; @(posedge clk) disable iff (!sig1 && sig2) |-> sig3; endproperty a_assertion_name: assert property(p_prop_name);
As I tri to compile using
vlog I get the following error:
** Error: (vlog-13069) sva/compx_sva.sv(34): near "|->": syntax error, unexpected |-> .
I checked the syntax and to me it looks alright. Any ideas why this should not work?