I've been reading on computer RAM and CPUs. I came to the conclusion that most RAM today use arrays of DRAM while CPU registers and caches use SRAM. 1 bit DRAM is a circuit with one capacitor and 1 transistor which controls the flow of charge in and out of the capacitor.

When the transfer from RAM occurs the CPU places the address required on the address bus and the RAM controller "opens" the transistors of the bits specified by the address.

If containing a charge, the capacitor will then discharge onto the data bus to the capacitor of the 1 bit register.

My question is about the requirements of the register state when the transfer occurs. If the bit of the register is set, then even if the RAM capacitor contains a charge, it will not discharge onto the data bus. The operation is thus not necessary.

Another situation is one where the register is set while the RAM bit is not set. If the path is open between the 2 capacitors then the charge will be transfered from the register to RAM which is not the required behavior.

I think of it as with the following circuit:

enter image description here

Is it the right way to think about memory transfers in computers?

Is the register grounded to 0 before the transfer occurs?

  • 3
    \$\begingroup\$ Didn't read the question, but your PSU is shorted. \$\endgroup\$
    – Eugene Sh.
    Commented Oct 8, 2020 at 19:45
  • \$\begingroup\$ @EugeneSh. can you edit the question with the actual correct circuit \$\endgroup\$
    – user123
    Commented Oct 14, 2020 at 12:59
  • 2
    \$\begingroup\$ This diagram is totally wrong and not the right way to think about "memory transfers". Learn about logic gates. \$\endgroup\$ Commented Oct 14, 2020 at 16:42
  • \$\begingroup\$ @user253751 I know this isn't the right circuit. I wanted the correct circuit without short circuit that does what my example does without modification. Should I just add a resistance to avoid the short circuit? \$\endgroup\$
    – user123
    Commented Oct 25, 2020 at 19:09
  • \$\begingroup\$ @user123 You should learn about logic gates and try building some circuits with logic gates. I recommend Logisim or one of its forks. \$\endgroup\$ Commented Oct 26, 2020 at 9:38

2 Answers 2


The situation is far more complex than this. The DRAM has sense amplifiers and bus drivers that provide a strong logic level output signal. There are also several layers of logic between the DRAM output and the 1-bit register. A full answer would be quite broad and lengthy, but you should start by studying computer architecture.

  • \$\begingroup\$ But at some point the charge will be amplified and transferred onto the data bus. Logic in between is important but if you have a simple processor built on a breadboard then is it the right way to implement memory? I heard of some students building an 8 bits processor. How do these students go about building RAM memory? \$\endgroup\$
    – user123
    Commented Oct 25, 2020 at 19:14
  • \$\begingroup\$ I suspect that the simplest way to implement RAM on a breadboard is to buy a static RAM chip and plug it in. \$\endgroup\$ Commented Oct 25, 2020 at 19:32
  • 1
    \$\begingroup\$ In which book or resource is this topic covered? Maybe you can consider adding that to your answer? \$\endgroup\$ Commented Mar 3, 2021 at 5:42
  • \$\begingroup\$ @ShashankVM One could start with en.wikipedia.org/wiki/Dynamic_random-access_memory and the references listed therein. \$\endgroup\$ Commented Mar 3, 2021 at 16:28
  • \$\begingroup\$ @ElliotAlderson Thank you \$\endgroup\$ Commented Mar 3, 2021 at 16:38

Is it the right way to think about memory transfers in computers?

no. In no data bus I can think of, a data-storing capacitor would be discharged directly to the bus to drive it - I mean, that would mean that each of the RAM cells would have to store an incredible amount of energy, just to "swing around" the bus.

Instead, there's always a readout or sense amplifier. Whether there is one per cell, or one for the selected line, depends on the technology (with modern memories, you practically have to have the amplifier extremely close to your data-carrying capacity).

That reads out the bit, amplifies it, sends it down a long line of logic. At the end of that stands a bus driver, and that's what's finally driving the bus.

There's never a direct electrical path between any processor part and the memory cell. That wouldn't even work – electricity can't flow fast enough. (Your PC CPU might be clocking at 4 GHz. In the time of a single clock cycle, you can't even bring an electromagnetic wave the distance from a CPU to the memory. Speed of light is a natural limit.)

  • \$\begingroup\$ I guess you are right since you seem to know more than I do. But when will the data actually be transfered. I think that memory read is a few clock cycles. Is the memory temporarily stored in a data buffer in the RAM controller? Otherwise the charge of the capacitor, even though amplified, will have to be transfered to the register at some point. \$\endgroup\$
    – user123
    Commented Oct 25, 2020 at 19:20
  • \$\begingroup\$ there's multiple stages at which things are stored intermediately. There's no "charge" transfer on the memory bus of a modern computer; that's already fast enough that you should be thinking of the bus-driving end as something emitting an RF signal into a transmission line, and the receiving and as actually something that has to receive. Really, so many layers between your transistor storing the bit and the register in the CPU, they aren't even remotely coupled. \$\endgroup\$ Commented Oct 25, 2020 at 20:45
  • \$\begingroup\$ I doubt there is "multiple stages" where things are stored intermediately. That would slow down a lot the RAM and be expensive. Processors and RAM aren't using radio waves they don't have receivers and transmitters. The instruction needs to be done before the next instruction since it could rely on the register content. \$\endgroup\$
    – user123
    Commented Nov 3, 2020 at 15:09
  • \$\begingroup\$ @user123 you're plainly wrong. Nothing in this needs to be done in one cycle, there's multiple stages because it doesn't work otherwise. \$\endgroup\$ Commented Nov 3, 2020 at 15:46
  • \$\begingroup\$ I know there are multiple stages but I doubt data is stored intermediately at these stages. I found a pretty nice book on this subject. I'm gonna read it eventually. amazon.com/CMOS-Memory-Circuits-Tegze-Haraszti/dp/0792379500 or a downloadable version: b-ok.cc/book/461479/92e467?redirect=32853093 \$\endgroup\$
    – user123
    Commented Nov 3, 2020 at 19:45

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