5
\$\begingroup\$

I'm trying to design a simple bandpass filter with fast settling time after powerup. I have tried several methods and in every case am finding limitation between requirements of HPF frequency, gain, and powerup settling time. I am hoping to learn if my limitation is due to my requirements or if there might be a circuit topology I haven't considered.

At a high level the application of this circuit is to be a rudimentary sound level meter for specific frequency range. The plan is to take a signal from MEMs microphone, amplify/filter it, and then read the output via a fast ADC built into my MCU. The accuracy requirements are very low and the design is working well, but requires a 35ms delay before signal settles which is too long for this application. The MEMs mic I am using is Knowles SPU0410LR5H-QB, which biases the signal at ~0.7V. The output is stable after approximately 0.5ms.

The approximate specifications I'm designing towards are:

  • Passband: 85Hz-500Hz
  • Gain: 37 V/V
  • Powerup Settling Time: <10ms

Here is the circuit that is currently working, but requires a 35ms settling time: Existing Circuit

Note that here the powerup settling time is dependent upon both HPF and gain settings. I'm a little confused here because I believe that the delay is due to charging C1 through R1+R2, however that would be a time constant of 71ms (e.g. 213ms to being mostly settled), while I'm finding the signal settles within ~35ms. Irregardless, I find that reduction of C1-R1-R2 does reduce my settling time, however to get time under 10ms I need to cut gain in half and double HPF which is quite significant of a deviation from my desired spec.

My leading option right now is to use a non-inverting amp and let it cut out half of the signal. The issue with passing the full signal is adding a resistor bias increases the delay and this design does not have room for a dual-supply rail. Note that I've doubled the gain here to account for having only half the signal. The other consideration is that the LPF will distort the half-wave signal, but I believe this is fine as long as I only track the peak voltage. The powerup settling time is independent of gain and although it is dependent upon HPF frequency, at 85Hz it is just under 10ms. Non-Inverting amp

I don't want to make my description too long, but here is a brief overview of some of the other options I've considered:

  1. With mentioned inverting amp circuit, I have tried adding a FET between IN- and IN+ controlled by the MCU at powerup. After optimizing the length of the control signal I find it still takes ~20ms before signal settles. Although the signal is never large enough to overcome the FET's body diode, I'm not a big fan of this approach of having a FET linked to the signal path.
  2. I have tried an IGMF filter with F0=250Hz, Q=0.707, and G=37. Although simulation showed a 6ms step response settling time, I find ~20ms settling after powerup when I breadboarded the circuit.
  3. I have tried a 2-stage approach with filtering in first stage and gain in second stage, however the second stage requires AC coupling capacitor and bias resistors which create an additional HPF stage and additional delay.

I'm happy to provide circuits on any of these if anyone would find it beneficial.

I think the non-inverting circuit will be okay, but thought it would be wise to reach out to this forum to see if I can gain a better understanding of the limitation and see if there might be an approach I haven't considered. Hopefully I'll learn something here and others will find the topic useful as well. I appreciate any insight I might receive.

EDIT: Here is the schematic and Scope captures of the IGMF Filter I tried: IGMF Filter Here are scope captures of the response with CH1 (yellow): Power rail CH2 (blue): Input signal CH3 (pink): Output This is powerup with the mic: IGMF Filter, Powerup Capture This is a step response from my function generator: IGMF Filter, Step response

\$\endgroup\$
7
  • 1
    \$\begingroup\$ 1. Reduce the series impedance: Use a low output impedance buffer for U2, eg a voltage follower opamp, then do the DC decoupling in the next stage. 2. Reduce the voltage difference in the decoupler cap, eg. by biasing the mic reference voltage or by changing virtual ground reference voltage for the amplifier. 3. Try to get rid of this decoupling cap, and see if you can make it a DC coupled amplifier circuit, probably correcting the DC bias in a later stage. 4. You mentioned 0.7V bias, which makes me think about an emitter follower stage. Low output impedance and a 0.6'ish voltage drop. \$\endgroup\$ – jippie Oct 10 '20 at 20:50
  • 2
    \$\begingroup\$ Bias In+in the first cct to 0.7V to match the mic output. Then C1 doesn't have to charge to Vcc/2-0.7V. (If you can live with reduced dynamic range in the opamp output since it's no longer symmetrical)). \$\endgroup\$ – user_1818839 Oct 10 '20 at 21:38
  • \$\begingroup\$ I like @Brian 's approach. The filter has a wide bandpass so it will be better designed as a composite with a combined HP and LP component rather than all-as-a whole, which works better with a narrower width. But the passive RC time constant for the HP part is just going to be a pain as \$5\tau\$ or so for settling is not going to go away. The pre-bias on the (-) input will save some time. Maybe enough, if you are careful. An active "start-up" circuit could be added, I suppose. But it's work and cost and space, etc. \$\endgroup\$ – jonk Oct 11 '20 at 3:10
  • \$\begingroup\$ If you short your op-amp's in+ and in- with a FET forget about the circuit working sensibly ! \$\endgroup\$ – Graham Stevenson Oct 11 '20 at 12:47
  • \$\begingroup\$ Thanks for this feedback. The problem I found when attempting a 2-stage approach was that the RC network formed by the bias resistors and decoupling cap caused significant settling time delay, however I suppose if I only use the first amp as a buffer there won't be significant delay there. I like your idea @Brian of using a lower reference voltage to match the mic's bias, however won't that voltage still need to make it through the large resistance of the feedback network? \$\endgroup\$ – TFD_Jon Oct 12 '20 at 3:04
2
\$\begingroup\$

Your problem is related to "integrator windup"*. It's what happens when a linear system goes non-linear (in this case by clipping) and stuff like phase and impulse response are out the window. At this point the integrating components in the feedback loop (ie, caps) will integrate an error signal which is garbage and it takes a while to get rid of.

Optimizing the filter impulse response for quicker settling will help shorten the settling tail, ie what happens AFTER it comes out of clipping. But when it is clipped it is no longer linear, so optimizing its linear behavior is not useful.

I have tried adding a FET between IN- and IN+ controlled by the MCU at powerup.

The purpose of the FET is to charge the cap. Here's an example for the non-inverting circuit:

enter image description here

Input is a step on top of a sine. Blue is original, red uses the FET to charge the 220n cap at powerup. It settles in less than 100µs, assuming the source has low impedance (I put in a 100R resistor for source impedance). Since MEMS microphones have internal amplifier, I expect lowish impedance. Note you don't have to use a FET, a microcontroller pin will do (switch to output 0 then high-Z) although it might inject some noise in the signal.

However I don't like the non-inverting circuit because it only processes half the peaks and will clip on the other half. Also if the opamp's offset is of the unlucky polarity, you get no output signal as long as input amplitude is below offset.

Inverting configuration:

enter image description here

Here a LED (or any diode with a Vf a bit below Vcc/2) shorts the 147k resistor when there is a bit too much voltage on it, which charges the 470nF cap a lot faster. If you put 2 diodes in antiparallel, it will also work for the other polarity and quick-settle instead of clipping after any step at the input... at the cost of a bit of voltage headroom on both sides.

Note shorting both inputs of the opamp with a FET will only make it clip, either up or down depending on its input offset voltage. So that didn't work. You have to short the high resistance that makes charging the cap slow, ie the 147k resistor.

enter image description here

That seems nice. Note I used a Cheat-FET with a magic driver courtesy of the simulator. You'll need a real FET switch. You could even have the micro look at the ADC samples, and if they look like the opamp is clipping, have the software flip the FET switch to help it come out of clipping much faster.

The 4k resistor still limits the current which still keeps it slow. So let's move a wire and let the switch short it too. When the FET is ON the opamp should still work pretty much as a follower.

enter image description here

It works, and it needs a much shorter ON-time on the switch, like a couple hundred µs. That should solve your problem.

Doing the same on the multiple feedback topology would require one extra switch since the two problematic resistors don't share a pin so it's not possible to short both with one switch.

  • = Integrator Windup is what happens when a badly designed audio amp clips:

enter image description here

Green is what it would look like without clipping. Red is actual output (well, actual as hand-drawn). Just because the amp is clipping doesn't mean the capacitors at various places, and especially compensation and feedback, stop processing the error signal (hatched area) which gets integrated. So at point 1 although it should do its best to go out of clipping, it won't decide to do so until that integrated error signal (ie, charge in caps) has been purged, which occurs at point 2 when the amp goes from nonlinear back to linear. By then the point where the output should be has moved quite a bit, so it immediately goes back into nonlinear (slew rate limiting in the other direction) which sometimes involves saturating a BJT, so it overshoots, waits until said BJT goes back to linear, and finally resumes linear function... If the output stage is rail to rail, and with a bit of luck, the lower transistor will conduct while the upper is still fully saturated, shorting the supply, and while you stare at the scope screen, smoke happens.

\$\endgroup\$
6
  • 1
    \$\begingroup\$ Nice answer (+1). I told OP that clipping is the culprit, and he saw if, too. He also said the mic has an output impedance of 4k, so tweaking the RC values might come in handy if this is taken into account. \$\endgroup\$ – a concerned citizen Oct 13 '20 at 19:43
  • \$\begingroup\$ Thanks! 4k is pretty high... would need to reduce cap values, increase resistors in the filter, maybe use FET opamp... \$\endgroup\$ – bobflux Oct 13 '20 at 20:06
  • \$\begingroup\$ Thanks @bobflux, this is a very detailed response. I haven't heard of 'Integrator Windup' before so I have some research to do, but I think you've pointed me in the right direction! \$\endgroup\$ – TFD_Jon Oct 13 '20 at 20:33
  • \$\begingroup\$ Regarding your more detailed comments, I'm not finding this windup problem with the non-inverting amp. No FET is needed here as this setup naturally settles within ~8ms and is mostly good except for only passing half the signal. Perhaps my understanding isn't fully there, but I was thinking the reason this was settling so much quicker was because there's no capacitance to charge (the DC blocking cap is not experiencing any current as it dead-ends into the non-inverting input). \$\endgroup\$ – TFD_Jon Oct 13 '20 at 20:37
  • \$\begingroup\$ Regarding the inverting setup notes you have, the reason I didn't want to put in a diode or FET into the feedback path is then I would have to ensure the gain is low enough to not develop more than 0.7V (or wherever the body diode/regular diode starts leaking) from output to input which is a concern. The part you provided for analog switch is very intriguing as it appears to somehow avoid the body diode inherent in a FET. I don't see how it does this but I'll have to order and try it out as I do agree your last circuit is quite ideal (if there's no body diode concern) \$\endgroup\$ – TFD_Jon Oct 13 '20 at 20:46
1
\$\begingroup\$

The way I design active filters is with this tool from analog devices. https://tools.analog.com/en/filterwizard/ It makes the design process super easy and very fast. There's a lot of options that they give you as far what you want you step response to look like and component selection. I highly recommend this to anyone doing active filters. The only downside is it's for analog devices and LT parts only. But you can easily sub those out for something similar.

\$\endgroup\$
2
  • \$\begingroup\$ If only any of those circuits resembled a 'filter' as I understand one. \$\endgroup\$ – Graham Stevenson Oct 11 '20 at 12:49
  • \$\begingroup\$ @bunker89320: The filter design software is handy, but it doesn't address the question being asked. The problem is that a given filter takes too long to reach normal operation after power on. The design tool doesn't address that. \$\endgroup\$ – JRE Oct 13 '20 at 16:59
1
\$\begingroup\$

There are good sugestions in the comments, but there is a way to design a filter for its fastest settling time. What I mean is you're opening your question with:

I'm trying to design a simple bandpass filter with fast settling time after powerup

But the settling time is not only when you're powering up. It happens everytime the input is no longer constant. Everytime the signal changes its amplitude or frequency there is a transient moment defined by the filter's impulse response. So, while using tricks such as the ones mentioned in the comments, with polarization, might work at power up only, they will not work during the usage. Unless, as mentioned, your signal is constant, i.e. a fixed amplitude and frequency sine, in which case this answer is reduced to a simple fast startup transient -- valid at power up, too.

Since you're only aiming for a 2nd order, then you can use the generic transfer function of a 2nd order bandpass and determine its impulse response:

$$H(s)=\frac{\frac{\omega_p}{Q}s}{s^2+\frac{\omega_p}{Q}s+\omega_p^2}\stackrel{\omega_p=1}=\frac{s}{s^2+\frac1Qs+1}$$

There are three possible formulas for the impulse response, underdamped, critically damped, and overdamped:

$$\begin{align} h_1(t)&\stackrel{Q>\frac12}=\left(Q\cos{\sqrt{Q^2-4}t}-\frac{Q^2}{\sqrt{Q^2-4}}\sin{\frac{\sqrt{Q^2-4}t}{2}}\right)\text{e}^{-\frac{Qt}{2}}\tag{1} \\ h_2(t)&\stackrel{Q=\frac12}=\left(Q-\frac{Q^2t}{2}\right)\text{e}^{-\frac{Qt}{2}}\tag{2} \\ h_3(t)&\stackrel{Q<\frac12}=\left(Q\cosh{\sqrt{Q^2-4}t}-\frac{Q^2}{\sqrt{Q^2-4}}\sinh{\frac{\sqrt{Q^2-4}t}{2}}\right)\text{e}^{-\frac{Qt}{2}}\tag{3} \end{align}$$

Out of these, \$(3)\$ has the laziest reponse, \$(1)\$ will oscillate, while \$(2)\$ seems the most appropriate. But if you account for the fact that the settling time is considered as the time it takes for the oscillations to be damped below a certain percentage1, then \$(1)\$ becomes a candidate. Therefore \$Q\$ can be slightly more than \$\frac12\$, and the oscillations will precede the convergence, while being inside the required value. It may sound a bit vague, so here's what I mean:

test

The traces are for Q=[0.5:0.01:0.55], in order: black, blue, red, green, pink, grey. Seeing that you're talking about many ms, I decided to go for a 0.1% value, though you're welcome to choose whatever value you wish. The bottom blot has the step response, and you can see that the peak is around 0.7 V. 0.1% of this would mean 0.7 mV, so the upper plot shows a zoomed version around the ±0.7 mV range. Black means critically damped, and grey means 0.55, and you can see how it oscillates just a little bit below the -0.7 mV threshold. Which means a slightly less value than 0.55 can be chosen. Note that, even if the common term for all the three responses is \$\text{e}^{-\frac{Qt}{2}}\$, that's not enough to determine the time it takes to reach the settling time, since for \$(1)\$ and \$(3)\$ there are either oscillating, or hyperbolic terms that are multiplied by that.

For the sake of discussion, let's assume the grey trace is right on cue. Then, while the black trace reaches the condition, +0.7 mV, at ~8 ms, the grey trace does it at ~5.5 ms. Therefore this filter would give the best settling time, for the given condition.

But now, the bandwidth changed. Your requirements were \$f_1=85\,\text{Hz},\;f_2=500\,\text{Hz}\$, which results in \$f_c=\sqrt{85\cdot 500}\approx 206\,\text{Hz}\$ and \$BW=|f_1-f_2|=415\,\text{Hz}\$, and the quality factor is directly related to the bandwidth here, \$Q=\frac{BW}{f_c}\$. Which means that, for \$Q=0.55\$ the bandwidth is \$BW'=\frac{206}{0.55}\approx 375\,\text{Hz}\$, or \$f_1'=91.2\,\text{Hz}\$ and \$f_2'=466\,\text{Hz}\$. If you're willing to live with this change, then the next part is also for you. Otherwise, you're stuck with the fixed value of \$Q=0.497\$. And this for a 0.1% settling time. For 1%, things can get even tighter.

To build it, there are many options, I'll choose the multiple feedback topology, partly because a readily available tool can be found here. Below is a comparison between the mathematical tansfer function with \$Q=0.55\$ (V(y)), and the resulting MFB bandpass, as calculated in the link above from \$f_c=206, K=-35, Q=0.55\$ (V(x), plotted negative because of the gain):

final


More details came out, such as the mic gives 0.7 V at startup, around 44 mV peak signal, and that its output impedance is 4 kΩ. As mentioned in the comments, and in bobflux's answer, the high input level of the signal combined with the high amplification of the filter cause the opamp to saturate, which brings nonlinearities into play that have the effect of a longer startup time. One of the solutions I mention in the comments is to compensate for the 0.7 V with a diode tied at a negative rails, but placed instead of the grounding of the input resistive divider. Of course, this implies having such a rail, in which case the whole filter could be powered from a bipolar supply. But, in case there is such a possibility, here is how the virtually identical signals show up for an ideal transfer function (V(y)), for a bipolar supply filter (-V(x) to compensate for the negative gain), and for a single supply version with diode (V(z), to which 6 V are added to compensate for the DC):

alt


1Usually 1%, but you can set it to 0.1%, or whatever other value, except 0, because, in theory, the response is asymptotic, and in practice you'll wait more than you'd be wiling to.

\$\endgroup\$
11
  • \$\begingroup\$ Thank you @citizen. I follow your logic, and this is actually one of the methods I tried (I even found that same OKAWA tool). I used slightly different parameters, using Q=0.707 for maximally flat response and a shifted centerpoint of 250Hz to account for the lower extension of this wider band (HPF frequency is more important than LPF). But I found that although the step response was fast (OKAWA had it settling within 6ms), when I put the circuit on the breadboard I found when powering up the circuit it takes about 20ms to settle and the step response shows about 15ms. \$\endgroup\$ – TFD_Jon Oct 12 '20 at 2:36
  • \$\begingroup\$ I've edited my post to include details on the IGMF Filter. Values were calculated from that tool and I've double checked the breadboard. I've also measured gain and response to confirm the filter parameters are working as expected, just the settling time isn't matching. I appreciate if you might be able to see anything I might be missing here. \$\endgroup\$ – TFD_Jon Oct 12 '20 at 2:52
  • \$\begingroup\$ @TFD_Jon A filter that has a specific settling time for a step input cannot have a greater settling time at powerup unless there is a perturbance somewhere: input, on the way, output. You are saturating the opamp, there's no telling how it recovers after going through the roof. You seem to be driving it with a 1 V step input, but your amplification is -35, which means the opamp will behave unpredictably. Try a 0.1 V and you'll get what you bargained for. Furthermore, it looks like even in the 1st scope pic, something similar must happen at the input: a step that is much greater than -Vcc/35. \$\endgroup\$ – a concerned citizen Oct 12 '20 at 10:45
  • \$\begingroup\$ I would check the response of the microphone, alone, during power up. It may be that it has a large output impedance together with (maybe) a series capacitor to block the DC, but whose value can bring larger time constants into play. \$\endgroup\$ – a concerned citizen Oct 12 '20 at 10:46
  • \$\begingroup\$ Thank you @citizen, your saturation comment is spot on. When I change the step response to a 50mV signal, I see the response settle in about 4ms. The larger the step voltage, the longer the saturated output holds. The reason why I tested with an 0.7V step is because this is what the mic does on powerup as it raises its signal output to the bias voltage. I'm not interested in detecting this step, but this is what I need to avoid at powerup to get quick settling. Can you think of anyway to 'ignore' the 0.7V jump to bias voltage on powerup? \$\endgroup\$ – TFD_Jon Oct 12 '20 at 23:23

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.