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This question has been asked before but there are too many conflicting opinions.

For a 2-layer board with a 3V3 polygon pour on the top layer and a GND polygon pour on the bottom layer, how should power connections be made to IC pins and decoupling capacitors?

I know there should be separate vias for the IC's GND pin and the GND pad of the decoupling capacitor, but what about the power pins? As I have it now, the IC pin and the capacitor pad are connected by the polygon pour and a separate trace. Should I get rid of the trace or remove the direct connection from the IC pin to the polygon pour?

Guidelines from TI seem to suggest the power should hit the capacitor first and then go to the IC via a trace (see figure 12 in https://www.ti.com/lit/an/scaa082a/scaa082a.pdf); their advice is "Make sure that the signal must flow along the capacitor." I have also seen people who know what they are doing say not to use a trace (http://www.sigcon.com/Pubs/news/9_07.htm). What would you do?

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We had a discussion on this on an answer on here a while back. You can read it here: Does ground pour circumvent bypass capacitors?

The conclusion I came to was that:

"Hitting the pad first" doesn't matter unless your frequencies are so that you are essentially doing RF in which case you will also be worried about a lot of other stuff the the width, thickness, length of your traces and the way your traces bend. At this point, it is a careful balance between everything and everything else (the factors mentioned above vs hitting the capacitor first to prevent waves from clashing and interfering with each other.

In cases where it doesn't matter, your first priority should be to make the loops and trace lengths between the capacitor and components as small possible. It can also make routing a lot easier (at least on a 4+plane board where you can just toss all the bypass caps under the IC and run each cap terminal and power pin straight to a plane through a via).

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  • \$\begingroup\$ So, essentially, connecting both the IC pin and the capacitor pin directly to the top pour is every bit as good as running a separate trace between the IC and cap? I know the goal is to minimize inductance and am wondering what the inductance of a fat trace vs. the three/four thermal reliefs would be. \$\endgroup\$ – Michael Lindell Oct 11 '20 at 21:47
  • \$\begingroup\$ @MichaelLindell Fat trace is lower inductance, obviously, but I do not know the numbers. Frankly, on a two layer PCB there are so many other dominating compromising factors something like a thermal relief isn't going to matter. A thermal relief makes soldering a lot easier though (though I tend not to use them). \$\endgroup\$ – DKNguyen Oct 11 '20 at 21:52
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Aaarrgghhh !

You're OVERTHINKING.

Sure, use thermal breaks for leaded parts and locate the decoupling caps close to the power pins with a connection to both planes as close as you can to their terminals. End of.

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  • \$\begingroup\$ I kind of thought so :). Is the "goal here is to keep the switching currents from the IC out of the power planes" in this answer not correct? electronics.stackexchange.com/a/233537 \$\endgroup\$ – Michael Lindell Oct 11 '20 at 21:44
  • \$\begingroup\$ You got it. Problem solved. \$\endgroup\$ – Graham Stevenson Oct 11 '20 at 23:00

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