I am currently trying to design a 16 nibble RAM on logisim, whereby it takes 4 data input lines.

However, what I am having the most trouble with is converting the 4 address lines into a single input, such that the RAM circuit should read a 4-bit piece of data as input and set this as the value of the nibble that is defined by the address bits.

For example, if Data = 1000 and Address = 0011, then in the next Clock cycle the value of 4th nibble of the RAM should become 1000, and also this value should be displayed on the output.

I know it involves a multiplexer, but what would act as the 4 selector bits?

  • \$\begingroup\$ Welcome to the site. The middle section reads like a homework question. Is it? If not, what is it for and why? Background helps a question get a better answer. \$\endgroup\$ – TonyM Oct 12 '20 at 22:43
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    \$\begingroup\$ The address lines are the selector bits \$\endgroup\$ – Chris Stratton Oct 12 '20 at 22:44
  • \$\begingroup\$ @TonyM Hello, Yes, it is a circuit homework that involves logisim. \$\endgroup\$ – anonymouseeeee Oct 12 '20 at 22:50
  • \$\begingroup\$ Are you building the RAM from individual registers, or are you using the 'RAM' memory device? \$\endgroup\$ – Bruce Abbott Oct 12 '20 at 23:41
  • \$\begingroup\$ RAM is addressable, that’s the random feature. in R, if it only had chip select and needed a 1 of 16 Decoder, it wouldn’t be RAM \$\endgroup\$ – Tony Stewart EE75 Oct 13 '20 at 2:30

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