I designed a circuit that requires buffers with the control gate (not like the ic's that have the control that will make every buffer turn on or off) . I am wondering how this works, and how it can be implemented with common npn transistors. Is the control just placed on the VCC of each buffer, therefore disabling it without power or is it something more complex?
No, the control definitely does not disable the power. That would leave the output in an in-determined state, either floating or pulled low, or worse: something inbetween, or even oscillating.
Think of the output of a logic gate as two controlled switches, one to ground and one to VCC. A normal gate always has one or the other switch closed. A tree-state output has the extra option of neither switched closed. Externally this results in an inactve (high impedance) state, but internally this is an active state, both FETs (switches) are actively forced to their non-conducting state.
I don't think you can implement this effectively with only NPN transistors. At the very least you will need some resistors. If you really want to do this check this diagram from datasheet for an old-fashioned 74125 tri-state buffer.