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I was reading an article on how to this guy was generating a sine wave digitally. He had a DAC made out of resistors. What I'm unsure about is what type of dac it is? To me it doesn't look like an r-2r dac. enter image description here

I've noticed the resistors R20-R22 are the mirrior image of R23-R25, am assuming there is a particular reason for this?

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I can't say for certain without simulating the circuit, but it looks as though the circuit is designed to produce a certain waveform if the Q signals are switched through the sequence 000000 100000 110000 111000 111100 111110 111111 or the reverse. The symmetry of the resistors on the left and right side will cause the resulting waveform to likewise be symmetric. This approach may be used as the first step to generating a sine-ish waveform. It may also be used to reduce the level of high-frequency components in a logic-level waveform without causing timing distortion. For example, suppose one had a 115,200bps serial data stream that one wished to send out over a wire while minimizing radiated emissions. If one used an analog filter to remove the high-frequency components, a rising edge which is preceded by a long low time could be delayed by a different amount from a rising edge one which follows a short low pulse. By contrast, if one fed the signal into a shift register whose outputs drove a resistor network as shown here, and the shift register was clocked at e.g. 9.216MHz (baud rate times 8), such a circuit would reduce the quantity of signal components in the range from 115.3KHz to 4.6Mhz. It's much easier to design an analog circuit that will filter out stuff over 4.6Mhz while leaving 115,200-baud data undisturbed, than to design one which will has filter out stuff at 130Khz but leave the data undisturbed.

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    \$\begingroup\$ Actually, the complete pattern is 000000, 000000, 100000, 110000, 111000, 111100, 111110, 111111, 111111, 011111, 001111, 000111, 000011, 000001. In other words, the output of a 7-stage Johnson Counter, which has 14 states (one stage is not used in the output). If the resistor values are chosen correctly, the first 7 harmonics are automatically canceled out, making the filtering of the remaining ones to get a pure sinewave much easier. \$\endgroup\$ – Dave Tweed Jan 1 '13 at 2:46
  • \$\begingroup\$ @DaveTweed: I believe the symmetry of the pattern assures that all even harmonics will be eliminated, in addition to the first seven. A DAC like this one (assuming the resistors are correct) could be useful with a 7-bit Johnson counter, but as noted that's not the only use. There are many applications where digital data stream needs to be filtered before being sent over an analog medium, and a shift register feeding this style of DAC would be a nice way to achieve an FIR filter with zero frequency-dependent time distortion. \$\endgroup\$ – supercat Jan 1 '13 at 5:36
  • \$\begingroup\$ Yes, I should have said the first 7 odd harmonics, in addition to all the even harmonics. And yes, an FM clock signal sent into such a circuit produces a very nice phase-continuous FM sinewave at the output. I don't know about the FIR filter, though; it seems rather crude. \$\endgroup\$ – Dave Tweed Jan 1 '13 at 12:35
  • \$\begingroup\$ @DaveTweed: If each resistor was connected to one of a series of cascaded sample-and-hold devices, the circuit would behave as a rather nice five-pole FIR filter; indeed, any five-pole FIR filter with all positive coefficients could be implemented with the same circuit, just by changing resistor values. If the signal which would be fed into the FIR filter is a "digital" signal (meaning it will always be "high" or "low"), a digital shift register would behave equivalent to an analog sample-and-hold. I was't thinking in terms of FM; I was thinking of something like... \$\endgroup\$ – supercat Jan 1 '13 at 19:13
  • \$\begingroup\$ ...UART data, which is a non-periodic collection of high and low pulses with a well-defined minimum width. Using this type of filter on pulses whose minimum width was less than six clock pulses might cause some pulses to be the wrong length, or disappear altogether, but the length of all other pulses would be preserved with a maximum uncertainty of one clock period (and if the source is synchronous with the clock, the added uncertainty would be essentially zero). \$\endgroup\$ – supercat Jan 1 '13 at 19:17
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Much like any other DAC, the different resistors are used to generate different voltage levels. Each resistor represents a certain weight in the total voltage. The DAC word is placed to enable/disable the resistors, which results in a specific voltage at the input of the LT1007. Note that the fact that the inverting input is connected to the output makes it a unity buffer so that it can provide a low impedance output and therefore drive the circuitry that follows.

Take a look at the Data Conversion Handbook from Analog Devices. It goes to explain even the most primitive DACs which are not even electronic.

Another explanation is available here: Resistor Ladder

The actual values of the resistors depends on the resolution and other parameters that one wants to achieve with the DAC.

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