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I'm looking at the Digilent RS232 reference component available from http://www.digilentinc.com/Products/Detail.cfm?Prod=S3EBOARD for the Spartan 3E Starter Kit. I began putting together a testbench, but the VHDL code contains an 'inout' port.

I've been looking at the code for the RS232 component, and I don't see how the RDA port is ever an input port - RDA is "Read Data Available", which indicates that there is a word ready to be read; I see that as an output function. I thought it would be clear why this was 'inout' after reading the code, but I cannot see how this is an input function at all.

Any thoughts? Thanks for your help, all.

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1 Answer 1

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In VHDL, if a port is declared "out", it can be assigned to, but it can't be used elsewhere inside the module. Specifically, the assignment on line 155 would be flagged as an error:

OE <= RDA;

Making the port "inout" makes this usage allowable.

However, inout ports are "messy" for a number of reasons, and I try to avoid them wherever possible. Another approach is to declare a second copy of the signal (e.g., RDA_int) that is used everywhere inside the module, and then to assign that signal to the output port just once.

RDA <= RDA_int;
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  • \$\begingroup\$ Thank you so much, this is an excellent answer and a good trick for VHDL to avoid this problem. \$\endgroup\$
    – trayres
    Jan 1, 2013 at 21:44
  • \$\begingroup\$ "buffer" type also allows you to read the value you wrote without making the signal truly bidirectional. \$\endgroup\$
    – akohlsmith
    Jan 1, 2013 at 22:06
  • \$\begingroup\$ @AndrewKohlsmith I have always created internal signals for this purpose. Reading a few discussions about this, buffer port mode seems to be troublesome and it is said (I can't find the original source) that Xilinx discourages its use, as it could cause synthesis errors (e.g. here). Does anyone have an idea on what makes it different? In the HW implementation, I mean. \$\endgroup\$
    – Serge
    Jan 2, 2013 at 2:02
  • \$\begingroup\$ @Serge: Thanks, I knew there was a reason I was avoiding "buffer" too, but I couldn't remember what it was. \$\endgroup\$
    – Dave Tweed
    Jan 2, 2013 at 2:07
  • \$\begingroup\$ I've seen "vhdlguru"s blog posts before... he doesn't actually give specific reference giving proof as to where the problem is in terms of documented operation, a bug report or an SR, but I'm suspecting it's in ISE. I've had no problems, not with Quartus (Altera) nor with Modelsim. \$\endgroup\$
    – akohlsmith
    Jan 2, 2013 at 3:30

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