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This could be a misunderstanding but everything I have gathered and seen it looks like there's a disconnection on what the reference manual says.

On Pg. 2212, in the STM32H753ZI it states:

"The master clock rate is fixed to 256 x FWS, where FWS is the audio sampling frequency."

So according to STM32 the FWS is the audio sampling frequency.

On page 2225, an equation sheet is presented to the end user to show how to acquire the desired sampling frequency (FWS) based on the SPI kernel clock.

enter image description here

On page 2226, a table is shown for a cheat sheet to configure the registers to get the correct FWS frequency.

The settings I used are highlighted.

enter image description here

Then in practice this is what I have obtained.

The green signal is when the samples takes place. High is the half complete DMA trigger and theow is the complete DMA trigger. The buffer is 4 length long of uint16_t

The yellow signal is the FWS signal. As you can see it Is shown to be at 48kHz stated above in the table. However when calculating the sampling frequency of the green it's ~96kHz. The math below.

It takes 20.8uS to trigger at 2 samples according to the green signal, then in 1 second you will have 96ksamples.

I have tried using the FWS= 96Khz configuration and it gave me a sampling frequency of 192kHz using the same logic above. I am seeing a trend where the sampling audio frequency is actually FWS*2.

Can someone shine some light onto this to see if the logic is wrong or if is this actually correct?

enter image description here

CODE:

uint16_t RxBuff[4];
uint16_t TxBuff[4];
uint8_t TC_Callback = 0;
uint8_t HC_Callback = 0;
char uartBuff[8];
void DMA1_Stream0_IRQHandler(void) {
    if (((DMA1 -> LISR) & (DMA_LISR_TCIF0)) != 0){
        DMA1 -> LIFCR |= DMA_LIFCR_CTCIF0;
        TC_Callback = 1;
    }
    else if (((DMA1 -> LISR) & (DMA_LISR_HTIF0)) != 0){
         DMA1 -> LIFCR |= DMA_LIFCR_CHTIF0;
         HC_Callback = 1;
    }

}

int main(void) {
    init_Clock();
    init_I2S();
    init_Debugging();
    init_Interrupt();
    init_SpeedTest();
  while (1)
  {



      if (HC_Callback == 1){
          GPIOA->BSRR |= GPIO_BSRR_BS3_HIGH;
          HC_Callback = 0;
      } else  if (TC_Callback == 1){

          GPIOA->BSRR |= GPIO_BSRR_BR3_LOW;
          TC_Callback = 0;
      }


  }
}

UPDATE 1:

Changed the FWS = 96kHz based on the tables, ten changed the RxBuffer length to 2. Here was the result. So essentially the DMA triggers based on every 1 sample.

Even though it says 96kHz I am doubting it is. If every 2 sample triggers at 92kHz and every 1 sample triggers at 196kHz the sampling frequency is ~ around 192kHz. All this is saying 2 samples per / 10.51uS = 192kSamples/ 1 second

enter image description here

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  • \$\begingroup\$ Did you consider that using say 48kHz sampling rate means you get 48000 stereo sampes, 48000 for left channel and 48000 for right channel samples or 96000 samples total per second. And each sample for each channel may be a 16-bit word or 32-bit word depending on how the I2S transmission is configured. \$\endgroup\$ – Justme Oct 13 at 6:36
  • \$\begingroup\$ I did not actually! I was assuming no stereo data came through after I set the register bit for SPI_CFG1_FTHLV to be 1 data. I see so when I calculating for 192kHz its 96khz for each channel. I knew about the 16 bit word or 32 bit word. Thank you for the insight kinda new to this \$\endgroup\$ – Leoc Oct 13 at 6:57

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