I am designing a device which drives I/O with circuits powered off an isolated power supply. To protect against ESD shocks, I placed bidirectional TVS diodes with 60 V forward voltage (SMBJ60CA). I connected one end to the I/O net and the other to chassis ground.

Just before sending this design to layout, it struck me that the reference for the I/O (let's call it ISO_GND) and the chassis reference (GND) may be at very far-apart galvanic levels, which could easily cause a potential difference > 60 V. If I'm not mistaking, this could cause arbitrary biasing of the diodes.

Is this something to worry about? What is a better way to implement ESD protection?

Edit: added an image to illustrate Clamping

  • \$\begingroup\$ That's one common way to do it for class I products. How does your ISO_GND and GND get separated by 60 V? Class II product with Y-capacitors forming a divider as "ground"? \$\endgroup\$
    – winny
    Oct 14, 2020 at 9:41
  • \$\begingroup\$ If my reasoning is correct, the ground potential difference is unknown, as they are floating with respect to each other. Hence, they may or may not be separated by 60+ V. I believe I do fall under Class I btw \$\endgroup\$
    – privera
    Oct 14, 2020 at 10:19
  • 2
    \$\begingroup\$ Can you show with a schematic or block diagram? \$\endgroup\$
    – winny
    Oct 14, 2020 at 10:23
  • \$\begingroup\$ @winny did already. I hope it helps explain. \$\endgroup\$
    – privera
    Oct 14, 2020 at 15:17
  • \$\begingroup\$ How is ISO_GND generated? \$\endgroup\$
    – winny
    Oct 14, 2020 at 16:23

1 Answer 1


No, it's quite common to do this and in almost all cases it's better to have an ESD transient event shunted to the chassis. Chassis grounds can usually handle\shunt large currents better because they are lower impedance and usually closer to the ESD source.

In addition if the ESD transient goes through the PCB it could also cause common mode noise through a low impedance cable and cause noise or worse, so what you have shown will probably work best for your design.

If A and B really are coming into the PCB at 60V because of galvanic levels, it would could exceed the maximum voltage of whatever transceiver you are using (or digital I/O) and cause problems there. If this is the case it may be best to use a digital isolator with built in ESD protection.

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  • 1
    \$\begingroup\$ What you are saying makes sense to me for the most part. However, regarding the last paragraph, the transceiver device I'm using is isolated and is referenced to the external galvanic level (ISO_GND). Since the TVS diode is hooked up to the chassis ground, which is at a different galvanic level, I still worry the diodes would conduct arbitrarily if these two galvanic levels diverge too much. Does it make sense? \$\endgroup\$
    – privera
    Oct 15, 2020 at 12:42
  • \$\begingroup\$ @privera Isn't that the point though? \$\endgroup\$
    – DKNguyen
    Oct 15, 2020 at 14:07

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