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I am designing a circuit that has a voltage regulator supplying several ICs. The voltage regulator, sensor, and communication module all recommend capacitors from VDD to Ground (1µF, 100nF and 100nF respectively).

My understanding is that these capacitors will all be in parallel. If these devices are all within a few mm of each other, can I roll all the capacitors into one (1.2µF) capacitor from VDD to ground?

Communication Module requires 100nF cap

Sensor Requires 100nF cap

Voltage Regulator requires 1uF cap

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    \$\begingroup\$ Smple answer : Yes. \$\endgroup\$ Oct 14, 2020 at 18:32
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    \$\begingroup\$ Chances are it will work fine with 1 uF cap and omitting the two 0.1uF caps. But, caps are cheap. I would just put all three caps in, and place them as close as I can to the IC pins. Consider placing the caps on the opposite side of the PCB if it allows the cap GND to get much closer to chip GND. Put the via to the plane close to the IC and close to the cap. \$\endgroup\$
    – mkeith
    Oct 15, 2020 at 4:11
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    \$\begingroup\$ Depends on your di/dt of the load (and sources if switch mode) and the ESR and ESL of your capacitors. Have you tried to simulate it with parasitics included? \$\endgroup\$
    – winny
    Oct 15, 2020 at 9:55
  • \$\begingroup\$ @winny Ok so if there is a lot of current spikes and drops, then there is more need for local caps. \$\endgroup\$
    – Luminaire
    Oct 16, 2020 at 17:37
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    \$\begingroup\$ Pretty much yes. If you have a good multilayer layout with multiple sandwiched Vcc and GND planes, the local part becomes less important. If you can spare the space, keep them as local as possible. \$\endgroup\$
    – winny
    Oct 17, 2020 at 8:05

3 Answers 3

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For a low-frequency system like you’re working on, the value of the bypass cap is less important. Generally, for non-critical designs some bulk cap at the power supply entry combined with 0.1uF caps at the device pins is enough. The bulk provides input noise rejection for ripple, while the per-pin bypass shunts switching noise locally at the IC. Different tools for different jobs.

Rules of thumb for high-frequency pin bypass:

  • If you don't know what you're doing, just stick with one value for the pins (0.1uF.)
  • If you know a little, and you have a higher-performance design, use > 10x decades to avoid anti-resonance (1uF, 0.1uF, 1000pF for example)
  • Always place the smaller values closest to the pin to minimize inductance and loop area.
  • Sensitive analog pins can also benefit from a series ferrite.

Bypass Design Resources

I have a few free go-tos that I've found useful for designing power network bypassing.

Here’s a Murata guide to noise suppression that is pretty comprehensive. https://www.murata.com/~/media/webrenewal/support/library/catalog/products/emc/emifil/c39e.ashx It covers caps, ferrites and other suppression types.

Murata's SimSurfing is very useful for showing passives parameters. Try it here: https://ds.murata.co.jp/simsurfing/index.html?lcid=en-us. They don't have a mode that shows combined responses however.

The Kemet KSIM tool does let you try out mixed values. It was pretty buggy, but it's been overhauled recently. Try it here: https://ksim3.kemet.com/capacitor-simulation

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  • \$\begingroup\$ Interesting so the bypass pins are having a local effect that requires them to be near the device pins, it's not just about the total capacitance of the pin's net? \$\endgroup\$
    – Luminaire
    Oct 16, 2020 at 17:34
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    \$\begingroup\$ Yes, because the distance from the pin increases the overall inductance and loop area. The added inductance reduces the effectiveness of the cap. The Murata doc goes into this in more detail. \$\endgroup\$ Oct 16, 2020 at 18:06
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I'd ask myself what I know that the manufacturer doesn't. Different size capacitors have varying frequency dependent impedances. The combination will give better filtering than one big fellah.

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  • \$\begingroup\$ Great point, so I guess they aren't looking just at the capacitance of the line per se, but of specific filtering characteristics, so I can't just lump them together. \$\endgroup\$
    – Luminaire
    Oct 14, 2020 at 18:26
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Tiny SMT caps can be placed very close to the IC leadframe.

The leadframe will always have residual inductancee, because the internal bits of metal are NON_ZERO in size.

And onchip capacitances can vary from low picoFarads (small logic or analog ICs) between VDD and Ground, up to many nanoFarads of inherent onchip (well_substrate and gate_oxide_to_bulk) capacitances.

For quality bypassing, you need some losses in the external (non_silicon) capacitors.

Using Rdampen = sqrt(L /C) for 2nH and 2,000pF (2nF), you can see you need 1 ohm loss within the circulating_energy path. That is not at all likely in the external capacitors.

However ----- the onchip circulating_energy path includes SUBSTRATE LOSSES.

Thus the onchip path, which will be in parallel with the external resonant paths, is crucial in minimizing ringing.

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  • \$\begingroup\$ I see, so if I lump all of my capacitors into one, that would create a long path to the capacitors which is not ideal for ringing? \$\endgroup\$
    – Luminaire
    Oct 16, 2020 at 17:33

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