# Crystal load capacitance for low power applications

According to Silicon Labs' app note on microcontroller oscillator design, larger load capacitance on crystals increase power consumption and increase startup time.

What are the actual numbers like in terms of power dissipation? Would there be any practical benefits to use a 9 pF crystal over a 20 pF crystal? Are there any drawbacks?

What are the actual numbers like in terms of power dissipation?

Below are a series of diagrams I produced when investigating crystal oscillator power dissipation changes versus external drive resistance (R1) and loading capacitor (CL1 and CL2) changes. The equivalent circuit is a good place to start before jumping into the actual power dissipation: -

Changing values for R1 (250 Ω to 1500 Ω) with CL1 and CL2 fixed at 20 pF produces slightly different oscillation frequencies (phase shift = 180°): -

Images from here.

The crystal is modeled as shown in the top picture. The crystal equivalent circuit has been chosen to produce a theoretical series resonance at precisely 10.000000 MHz. That frequency is determined by the components inside the orange box. The image link gives more details if you need them.

The important thing to note from above is that the oscillation frequency is somewhat "R1" dependent. The oscillation frequency is produced when the phase shift = 180° i.e. adding a "perfect" inverter generates an overall phase shift of 360°. Further down I show how an imperfect inverter can increase power dissipation in the crystal.

Looking at the graph above, the stablest oscillation frequency is the one where the phase shift passes through the 180° point with the least ambiguity. This tells us that a higher drive resistance (R1) produces better crystal stability. A higher drive resistance also produces the least amount of power dissipation in the crystal. However, things look a little different when we vary loading capacitance. The next picture keeps R1 at 500 Ω and varies the loading capacitors: -

The conclusion here is that higher values of loading capacitance produces a more stable frequency (less ambiguity in the frequency that yields 180°) but, the power can be significantly higher compared to using small values of loading capacitor.

But the inverter gate used also can play a big role. If the inverter has stated propagation delays of (say) 10 ns, the required phase shift to be produced by the crystal is somewhat less that 180° i.e. it might be closer to 160°. The effect on power dissipation is shown below: -

The linked article explains that a data sheet propagation delay of 10 ns would strictly erode the required crystal phase shift by 36° but, because the gate is used in its linear region the overall delay might be about 50% of 10 ns leading to the crystal being required to produce a phase shift of about 160°.

Hope this helps. The subject is as deep as you want it to be. More loading capacitance equals better oscillation stability but it also equals higher power dissipation in the crystal that can also lead to oscillator frequency degradation.

<10 pF are common now with high accuracy are preferred for the reasons stated.

Then learning how to compensate for Cin and Cgnd stray capacitance are more important. leaving out a gnd underneath reduces stray capacitance to gnd.

Generally it is wiser to use an XO rather than an X with caps as the cost is reasonable, or if you prefer accuracy of 1 to 2 ppm TCXO, these are also cheap today ( unless there are reason why not in your assumption list TBD) (X=Xtal crystal)

Powers in the motional capacitance and series R are in xx uW levels with Cs in xxx nanofarads actually reach very high voltages between the Xtal lattice from Q=10k. This is not the logic inverter power.

• Thanks for the advice! I plan to use the "xtal crystal with caps" solution however, as an oscillator is about ten times the cost. Aside from ease of implementation and consistency, are there any other benefits from using XO? (I've made successful boards with oscillators but I'm now looking to minimize cost while maintaining good performance) Oct 15, 2020 at 6:20

It's a known fact that the oscillator needs a minimum (critical) current to start and maintain the oscillation.

What are the actual numbers like in terms of power dissipation?

Eric Vittoz explains this quite well in his paper about oscillator design. I'll not dive into the technical details but only the result.

The critical conductance for the oscillator to operate is given as,

$$\mathrm{ g_{m-crit} \approx (2\ \omega \ C_L)^2 \ R_{ESR} }$$

where $$\\mathrm{\omega}\$$ is the oscillator frequency in radians ($$\\mathrm{2\pi \ f_n)}\$$, $$\\mathrm{C_L}\$$ is the load capacitance, and $$\\mathrm{R_{ESR}}\$$ is the motional resistance of the crystal which is given in the datasheet (NOTE: This applies to CMOS oscillators).

And the operation current of the oscillator is approximated as,

$$\mathrm{ I_O\approx \ g_{m-crit} \ X_B }$$

where XB comes from running a zero- and a 1st-order Bessel function over the oscillation amplitude and the thermal voltage (VT = 26mV). As an example, XB has been calculated as approximately 4 for an assumption of the oscillation amplitude is 0.4V. I think you can calculate the operation current with these assumptions.

Would there be any practical benefits to use a 9 pF crystal over a 20 pF crystal? Are there any drawbacks?

The formula above helps to explain how the MCUs decrease the power consumption in, for example, sleep mode by decreasing the oscillator frequency down to a few tens of kHz or even a few hundreds of Hz. So, when the low-power consumption is a key requirement (e.g. for coin-cell-operated systems, where uA- or even nA-currents are important), using crystals with lower CL becomes vital.