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Please help me understand how such huge and complex devices like modern CPUs' are designed - would it be possible to see an example of some final circuit with billions of transistors made with Verilog/VHDL? All examples on the Internet show only small ICs. I would like to see how today's engineers manage "ultra-large-scale integration" designs for chips like CPU/GPU/ASIC on regular workstations. I would like to know how such humongous device can be managed effectively and by so many people.

I am aware of FGPAs, but I think that their workflow is much more predefined and doesn't lend itself to the same complexity. I am aware of the Verilog/VHDL pipeline and I haven't seen anywhere a demonstration with BILLIONS of transistors chips.

I would really like to know how teams manage such amount of complexity and how much is it being broken down into IP blocks. For example, how many lines or Verilog/VHDL is being written for one of Intel's i7 CPUs?

RISC-V looks interesting and if nothing was available on the mainstream ICs it would be also helpful to see some good CAD/GDS output from RISC-V.

The reason why I would like to see it, is I worked a lot with CAD software (AutoCAD, McNeel's Rhino) and it's always been very slow. Hope that getting some insight from EDA/ECAD could hint a path to use them more effectively.

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    \$\begingroup\$ If you browse the schematic of even an ordinary interface IP, like GMAC or USB, you'll find yourself sunken in a sea of gates. \$\endgroup\$ – Light Oct 15 at 12:49
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    \$\begingroup\$ There are many opensource core designs available that you can look into the guts of. However, if you want something that once was in real production, Oracle has actually released the Verilog source code and design docs for their UltraSPARC (OpenSPARC) T1 and T2 processors. They are both over a decade old, but still actual multicore "SMT4" designs. If you are looking for the "masks" for a large CPU like that, I doubt you'll find anything like that public. \$\endgroup\$ – Richard the Spacecat Oct 15 at 12:51
  • \$\begingroup\$ @Light thank you, I think that part of my problem is not knowing what keywords to look for. Thats helpful \$\endgroup\$ – Daniel Krajnik Oct 15 at 12:53
  • \$\begingroup\$ @Light would it be possible to see somewhere, maybe in some older model a complete assembled chip as well? \$\endgroup\$ – Daniel Krajnik Oct 15 at 12:54
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    \$\begingroup\$ Depending what you mean by "see", zeptobars.com/en has a lot of die shots for "complete assembled chips" that have been decapped so the metal+silicon can be seen. \$\endgroup\$ – pjc50 Oct 15 at 13:16
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I don't think such large ICs are designed directly in Verilog, no more than large software projects are written in assembly. I suspect the big makers, like Intel and AMD, have specialist compiler-like software that generates Verilog from much more high-level descriptions, such as register transfer languages.

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  • \$\begingroup\$ interesting, it would be so helpful to know what "tech stack" / tooling Intel and AMD has. Importantly, do you think they have a normal repository like Perforce, or more something custom like Google did? \$\endgroup\$ – Daniel Krajnik Oct 15 at 12:57
  • \$\begingroup\$ And also do you think that any part of the circuit is still drawn by hand or is EVERYTHING generate by code (RTL or Verilog)? \$\endgroup\$ – Daniel Krajnik Oct 15 at 12:58
  • \$\begingroup\$ No idea, but I don't see why they wouldn't be satisfied with Git. Re drawn by hand, again I have no real idea, but the lower-level power-related stuff seems like a plausible candidate for that. \$\endgroup\$ – Anton Tykhyy Oct 15 at 13:00
  • \$\begingroup\$ AFAIK only the higher-level floor planning (and I suppose the standard cells) are "drawn by hand", the rest is all automagic as far as typical digital designs are concerned. Not that I know anything about this though, just what I might've heard once; so all of this comment might be completely mislead. Please correct me. \$\endgroup\$ – Richard the Spacecat Oct 15 at 13:02
  • \$\begingroup\$ @RichardtheSpacecat interesting, and woud you be able to point me to some source to read more about how today's "automagic" works, by any chance? \$\endgroup\$ – Daniel Krajnik Oct 15 at 13:11
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The problem here is that the tech stack (knows as a flow) tends to be a trade secret and heavily NDA'd.

As a beginner asking an open-ended question, perhaps the most useful answer is a list of places to look for more information. The two big software vendors are Cadence and Synopsys. Both of them offer a full flow from RTL (and earlier) through to the polygons sent to the foundry ("GDSII" pronounced "G D S two", it's a file format). They produce lots of brochureware with pretty diagrams.

I would really like to know how teams manage such amount of complexity and how much is it being broken down into IP blocks. For example, how many lines or Verilog/VHDL is being written for one of Intel's i7 CPUs?

Quite a lot of the larger chips is on-chip SRAM, which adds a lot to transistor count while not appearing as very complex in the design phase. Similarly, things like GPUs have lots of identical execution units. Design once, paste lots of copies across the chip, then put a tie layer across the top.

Intel themselves will occasionally put out whitepapers and presentations in which they show block diagrams.

The reason why I would like to see it, is I worked a lot with CAD software (AutoCAD, McNeel's Rhino) and it's always been very slow

I have some bad news for you: I worked on some EDA software about a decade ago, and it was also incredibly time-consuming. Our startup offered a tool that would adjust your clock tree to reduce power by 10-20%. For a million gate design on the largest PC we could buy at the time it ran overnight.

Back then larger designs were generally broken down into 1m-gate sized blocks at the "floorplanning" stage, on the basis of what the team and tools were capable of managing.

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    \$\begingroup\$ Wow, thanks a lot for shedding light on performance, copy-paste strategy issues and the rest - very helpful. That's really heartbreaking that we put up with this workflow, this may sound spoiled coming from me, but I think that need for "instant gratification" is actually a virtue. Do you know if there have been any improvements since then, any new software frameworks that might have turbo-charged the workflow? \$\endgroup\$ – Daniel Krajnik Oct 15 at 14:28
  • \$\begingroup\$ It's a very small, conservative, uncompetitive market - there will have been incremental improvements, but no big disruptors. I think alternative HDLs like Chisel are starting to make inroads but the low level tooling remains as it is. Perhaps eventually an open FPGA toolchain will appear on which rapid public progress can be made. \$\endgroup\$ – pjc50 Oct 15 at 16:55
  • \$\begingroup\$ that would be great, fingers crossed. Hmm, and yes that's actually a really good point. \$\endgroup\$ – Daniel Krajnik Oct 15 at 18:11

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