Please help me understand how such huge and complex devices like modern CPUs' are designed - would it be possible to see an example of some final circuit with billions of transistors made with Verilog/VHDL? All examples on the Internet show only small ICs. I would like to see how today's engineers manage "ultra-large-scale integration" designs for chips like CPU/GPU/ASIC on regular workstations. I would like to know how such humongous device can be managed effectively and by so many people.
I am aware of FGPAs, but I think that their workflow is much more predefined and doesn't lend itself to the same complexity. I am aware of the Verilog/VHDL pipeline and I haven't seen anywhere a demonstration with BILLIONS of transistors chips.
I would really like to know how teams manage such amount of complexity and how much is it being broken down into IP blocks. For example, how many lines or Verilog/VHDL is being written for one of Intel's i7 CPUs?
RISC-V looks interesting and if nothing was available on the mainstream ICs it would be also helpful to see some good CAD/GDS output from RISC-V.
The reason why I would like to see it, is I worked a lot with CAD software (AutoCAD, McNeel's Rhino) and it's always been very slow. Hope that getting some insight from EDA/ECAD could hint a path to use them more effectively.