# Understanding the IRS10752 Datasheet

I am looking at implementing a high side N channel MOSFET driver for some power switching circuitry I am working on. Plenty of great looking driver chips are out there, but they all cost \$2.00 per part in small quantities. I am looking to spend less and came across the IRS10752.

The only problem is that the data sheet is a bit sparse when it comes to implementing a driver circuit using the IRS10752. It comes with a typical connection diagram and a simplified internal schematic, but I wanted to get another opinion on what the other parts in the typical application circuit actually do.

I've included an annotated version of the application circuit, the internal circuit, and a link to the data sheet below. I've also included my best guess on what each part actually does.

Best Guesses

• D_GD1: ????
• C_GD1: bypass capacitor for the IC's power supply
• C_GD2: reservoir capacitor for gate drive boost circuitry
• R_GD1: timing / current limiting resistor for gate source / sink

https://www.infineon.com/dgdl/irs10752lpbf.pdf?fileId=5546d462533600a40153567308ca276d

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C_GD2 is called the "bootstrap" capacitor. When the MOSFET is off it charges up to VCC<->Source voltage trough bootstrap diode D_GD1. When the MOSFET has to turn on the chip will connect VB to HO, effectively putting the charged capacitor in parallel with the MOSFET gate-source. As the MOSFET turns on the source begins to rise towards V_BAT(x)_BUS, but because the capacitor is referenced to the source it "rides up" along with the source voltage, so the gate is always at source+C_GD2 voltage, which keeps the MOSFET fully turned on. Since VB is now at a higher voltage then VCC the function of diode D_GD1 should be clear.

Note that in such a circuit the MOSFET should be turned off periodically to give the bootstrap capacitor a chance to recharge, it can not be used to keep the MOSFET on indefinitely.

C_GD1 is indeed just a regular bypass cap for the chip's power supply.

R_GD1 is usually added to prevent ringing due to parasitic elements in the gate drive circuit. It slows transition times and damps oscillations.

This is a high-side, single-channel gate driver IC with 100V blocking and level-shifting capability from <2.2V to 10V, while non-inverting.

This IC is just like the impedance of CD4000 logic except rated for 100V. Do not assume that any high side logic FET will work well with your reactive load. That would create a large negative spike on shutoff and may cause damage.

Do the Bode and RLC analysis with back EMF to ensure your design will not be prone to resonances, over/undershoot and other instabilities. Use the impedance of Vol/Iol = 300 typ to 600 Ohms max for example and higher on (Vdd-Voh)/Ioh with Ciss to estimate high side rise time with RC load fall time which may be variable.

PWM to load creates AC to C_GD2 and clamp diode F_GD1 to boost voltage for high side Vgs > Vbat. this was designed for a Pch high voltage, high side switches, unless your Vdd is greater than Vbat. this why dual Nch half bridges were made. the low side is PWM’d to create a boost voltage, Vb for the high side Pch so that Vb = Vbat+>3*Vgs(th). The full bridge then gives direction of bipolar polarity control while the low sides are used with PWM.