I am making a transmission gate using ALD1106 NMOS and ALD1107 PMOS model files. For -5V (to NMOS and +5V to PMOS), with input 5V, the output should come 0 as the transistors would be in off state. But the output is coming 5V.
What is working: When NMOS and PMOS voltages are +5V and -5V respectively, the source voltage is reflected at drain.
What is not working: When NMOS and PMOS voltages are -5V and +5V respectively, the source voltage is reflected at drain. The gate should be in switched off mode.
What I have tried: My target input voltage at source is sine wave of amplitude 1Vpp and frequency 1kHz. Now I know that, condition for switch to be off is Vgs (gate to source)<Vth (threshold). So for my case of sine input and supply voltage(which is + or -5 volts), the condition might not hold true as Vth is state to be around 0.8V in the spice file. So, I changed the sine input to 10Vpp to have a maximum of 5V. But the input is still getting reflected at output even in off condition.
Note about inverter: I have used the default inverter from [digital] in LTSpice component bank. To get +/- 5V, I have added "Vhigh=5 Vlow=-5 Ref=0" to the "value" line in the attributes of the inverter (and by attributes I mean when one right clicks on the inverter and gets a dialog box with some attributes like value, value2, spiceline, spiceline2)
ALD1106/1107 spice file contents:
Model file for ALD1106 and ALD1107 SPICE Level 1 .MODEL ALD1106 NMOS (LEVEL=1 CBD=0.5p CBS=0.5p CGDO=0.1p CGSO=0.1p GAMMA=.85 + KP=479u L=10E-6 LAMBDA=0.029 PHI=.9 VTO=0.8 W=20E-6) .MODEL ALD1107 PMOS (LEVEL=1 CBD=0.5p CBS=0.5p CGDO=0.1p CGSO=0.1p GAMMA=.45 + KP=206u L=10E-6 LAMBDA=0.0304 PHI=.8 VTO=-0.82 W=20E-6)
This is present inside a file named ald.txt that I am including using ".lib ald.txt" statement. Then I am using the default NMOS and PMOS from the LTSpice component bank and I am renaming them to ALD1106 and ALD1107 respectively to behave like the desired transistors.
What I expected: The output voltage to be 0 since switch is off, but output is same as input (as you can see two overlapping traces taken at input and output).
Netlist of my asc file:
* C:\Users\w\Desktop\LTSpice Models\Lab 5\Transmission Gate_Switch\Transmission_Gate.asc V1 N001 0 -5 A1 N001 0 0 0 0 N004 0 0 BUF Vhigh=5 Vlow=-5 Ref=0 V2 N002 0 SINE(0 5 1000) M1 N003 N001 N002 N002 ALD1106 M2 N002 N004 N003 N003 ALD1107 .model NMOS NMOS .model PMOS PMOS .lib C:\Users\w\Documents\LTspiceXVII\lib\cmp\standard.mos .tran 0.005 .lib ald.txt .backanno .end
Is there something beyond my current knowledge base that I missed or is it something silly that I am overlooking? Why is "off" state not happening.