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I am making a transmission gate using ALD1106 NMOS and ALD1107 PMOS model files. For -5V (to NMOS and +5V to PMOS), with input 5V, the output should come 0 as the transistors would be in off state. But the output is coming 5V.

What is working: When NMOS and PMOS voltages are +5V and -5V respectively, the source voltage is reflected at drain.

What is not working: When NMOS and PMOS voltages are -5V and +5V respectively, the source voltage is reflected at drain. The gate should be in switched off mode.

What I have tried: My target input voltage at source is sine wave of amplitude 1Vpp and frequency 1kHz. Now I know that, condition for switch to be off is Vgs (gate to source)<Vth (threshold). So for my case of sine input and supply voltage(which is + or -5 volts), the condition might not hold true as Vth is state to be around 0.8V in the spice file. So, I changed the sine input to 10Vpp to have a maximum of 5V. But the input is still getting reflected at output even in off condition.

Note about inverter: I have used the default inverter from [digital] in LTSpice component bank. To get +/- 5V, I have added "Vhigh=5 Vlow=-5 Ref=0" to the "value" line in the attributes of the inverter (and by attributes I mean when one right clicks on the inverter and gets a dialog box with some attributes like value, value2, spiceline, spiceline2)

My schematic:

Transmission Gate Schematic

ALD1106/1107 spice file contents:

Model file for ALD1106 and ALD1107
SPICE Level 1

.MODEL ALD1106 NMOS (LEVEL=1 CBD=0.5p CBS=0.5p CGDO=0.1p CGSO=0.1p GAMMA=.85
+ KP=479u L=10E-6 LAMBDA=0.029 PHI=.9 VTO=0.8 W=20E-6)

.MODEL ALD1107 PMOS (LEVEL=1 CBD=0.5p CBS=0.5p CGDO=0.1p CGSO=0.1p GAMMA=.45
+ KP=206u L=10E-6 LAMBDA=0.0304 PHI=.8 VTO=-0.82 W=20E-6)

This is present inside a file named ald.txt that I am including using ".lib ald.txt" statement. Then I am using the default NMOS and PMOS from the LTSpice component bank and I am renaming them to ALD1106 and ALD1107 respectively to behave like the desired transistors.

Output observed (for sine wave of amplitude 10 Vpp): Output

What I expected: The output voltage to be 0 since switch is off, but output is same as input (as you can see two overlapping traces taken at input and output).

Netlist of my asc file:

* C:\Users\w\Desktop\LTSpice Models\Lab 5\Transmission Gate_Switch\Transmission_Gate.asc
V1 N001 0 -5
A1 N001 0 0 0 0 N004 0 0 BUF Vhigh=5 Vlow=-5 Ref=0
V2 N002 0 SINE(0 5 1000)
M1 N003 N001 N002 N002 ALD1106
M2 N002 N004 N003 N003 ALD1107
.model NMOS NMOS
.model PMOS PMOS
.lib C:\Users\w\Documents\LTspiceXVII\lib\cmp\standard.mos
.tran 0.005
.lib ald.txt
.backanno
.end

Is there something beyond my current knowledge base that I missed or is it something silly that I am overlooking? Why is "off" state not happening.

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  • \$\begingroup\$ Add a load to your "transmission gate" output \$\endgroup\$ – V.V.T Oct 16 '20 at 5:15
  • \$\begingroup\$ Yes it worked with a 1000ohm load. Now, why did it? I mean shouldn't the schematic show proper behaviour without load. If I did the circuit on breadboard, I would not get a thought on connecting the load, I would directly measure it because that's my output. Why add a load? Ohk is it that when I will measure, my voltmeter will become the load and this is what I missed? \$\endgroup\$ – Prasanjit Rath Oct 16 '20 at 5:29
  • \$\begingroup\$ You get it right. Exactly -- when you measure, you load the output with the 'scope probe. Simulate the circuit with a 10MOhm load and it still works. \$\endgroup\$ – V.V.T Oct 16 '20 at 5:43
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These transmission gates are built with 4-pin MOSFETs for a reason: the 4th pin must be tied to the lowest (NMOS) or highest (PMOS) voltage potential. With these in mind, here's a reworked version:

test

Notice where the 4th pin of each MOS is tied up to. Also, there is no need for a loading resistance in this case: R is .stepped between 10k (on) and 1g (off), and the output is virtually the same. In real life, you would have some sort of load, though.

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    \$\begingroup\$ The datasheet for these devices even show this by bringing the NMOS and PMOS body nodes out to the V- and V+ pins respectively. I actually never knew they made devices like these outside of the old CD4007, so kinda cool to find out about them. \$\endgroup\$ – Ste Kulov Oct 16 '20 at 11:49
  • \$\begingroup\$ Here since, MOS' bodies are not shorted to sources, we have to consider body effect, right? \$\endgroup\$ – Prasanjit Rath Nov 13 '20 at 10:48

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