# N-MOSFET Gate to Drain short circuit configuration and Vgs

I notice that in solution manuals to problems like these, when the gate is shorted to the drain on an NMOS, Vds = Vgs. So Vds >= Vds - Vtn, making the MOSFET always in saturation.

I do not understand why this is, and have not been able to find a diagram that I could make sense of. How can we explain this more visually? Here is the problem this schematic came from. Microelectronic circuit design, 5th edition. • Is it an examination solution manual written by another struggling student? Can you give us a link or at least more details? Oct 17, 2020 at 0:42
• Why does the gate to source voltage become equal to gate to drain voltage, when shorted from gate to drain? Like in the schematic I posted. If you want the actual problem from the book I can add it but I thought posting book problems was off limits on here. Oct 17, 2020 at 1:14
• Many thanks for your reference of the book. I googled and found Chegg's cheat book. chegg.com/homework-help/…. Cheers. Oct 17, 2020 at 4:19

First of all, I'm sure you ment Vds >= Vgs - Vth for a MOSFET in saturation.

Vds is defined as the potential difference between drain and source, Vgs as the potential difference between gate and source. simulate this circuit – Schematic created using CircuitLab

By shorting gate and drain, they share the same potential. Therefore, Vgs = Vds. That much should be pretty obvios.

Now have a look at the output characteristics of a standard MOSFET below (graphic taken from this answer). Focus on one specific value for Vds. You can see how the drain current increases with increasing Vgs (or rather Vgs - Vth). If Vgsis smaller than Vth, the MOSFET is basically completely blocking. Once Vgs is larger than Vth, all MOSFETs more or less share the shown behavior. That is why plotting Vgs - Vth is more usefull to us than plotting Vgs right now. The saturation region is the region in the plot, where the drain current is independent of Vds and therefore is just a horizontal line. In the linear region, the drain current is dependent on Vds, and the MOSFET behaves roughly like an ohmic resistor.
Take a closer look at the red line seperating the regions (in reality, this is not a hard transistion but rather a soft change). This line follows the equation Vds = Vgs - Vth. Check it yourself!
At the point where it crosses the blue Vgs - Vth = 4V, Vds is also 4V. The same applies for other values.
If Vds is larger, we are on the right of the red line; in the saturation region. If Vds is smaller, we are on the left, in the linear region.

To be honest, I'm not sure if there is a deeper physical explanation for this formula or if it is just a convenient coincidence. However, keep in mind that it is not a hard boundary and the whole model of underlying theory of how a MOSFET operates just an approximation.

To sum it up, you should

• make sure you understand what the voltages Vds and Vgs mean in general and for your circuit
• then have a deep look at the output characteristics graph. At least for me, it was the hardest part to wrap my mind around the fact that three quantities are plotted in the same graph. Once you managed that, it becomes an increadibly useful tool while designing and analysing circuits.
• Your answer is excellent, and newbie friendly to me with IQ 97. I really appreciate your suggestion at the end of "taking deep look, ... wrap my mind around the fact that *three quantities are plotted in the same graph, ...". I studied a EE diploma ages ago, and I confess that when reading about linear/saturation region of BJT operation, I had not taken a deep enough look at the graph, and so I did not know, as you said, three quantities are plotted on the same graphs. / to continue, ... Oct 17, 2020 at 4:46
• At that time I only knew a basic graph with X- and Y- axis. I never thought that there can be a graph with three axis, X, Y, and Z! Oct 17, 2020 at 4:47
• to make sure I thoroughly understand your answer, I use the following MOSFET as a case study: IRL540N 100V N-Channel Power MOSFET Datasheet - Infineon: infineon.com/dgdl/…. I read the data sheet and I have two questions related to the linear/saturation region. The questions are written in the following picture: i.imgur.com/zNX2E4W.jpeg. I am designing switching circuits using this IRL540N. I would appreciate it you can answer my questions. Thanks a lot. Cheers. Oct 17, 2020 at 7:27
• For a detailed answer, you should start a new question. In short, measuring Vth with gate and drain shorted is just a useful convention, I guess (correct me if I'm wrong). It makes measuring and comparing of different devices easier. Your points a), b) and c) are all correct. Consering the graph: it actually only has two axis, but Vgs-Vth can be seen as a parameter which changes the curve. Oct 17, 2020 at 12:58
• I would like to clarify that my book defines threshold voltages as Vtn and Vtp. Not Vth. Theydo it to not confuse with thevenin voltage so that’s how i write it now. Excellent answer. Oct 17, 2020 at 16:56

Assuming Vdd is large enough, it is no different from driving Vgs with a separate voltage high enough to completely turn on the MOSFET so it conducts as much as it can and behaves as a switch (ie. a very low resistance) across the source drain.

In this configuration, the nmos is called an enhancement load, this makes the nmos act like a diode but the curve is follows a square expression instead of exponential, thus making it a non-ohmic resistor, as follows: One circuit where this is useful is one in which an enhancement load is placed on top and an nmos is on the bottom, the output is taken from between them, as follows: When the bottom nmos is turned off, the output will be Vdd - Vth. Turning the bottom nmos on will form a voltage divider, getting the output close to zero. This makes this circuit an inverter, although it is not a particularly good one, it is better than having a resistor as that takes a large amount of space on a chip. A better inverter uses a depletion nmos or CMOS, but that is not relevant here.

The circuit you provided with two depletion loads in series acts just like a voltage divider made out of two equal diodes, so the output voltage is half Vdd. This holds true if each enhancement load has more than its threshold across it, and makes current calculation easier as you only need to consider a single nmos with half the supply voltage. 