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I am trying to understand this example of single port memory where an 8 by 64 bit RAM is created. If I am understanding correctly, the section of code that says "reg [7:0] ram [63:0]" means that there is 64 memory units that can contain 8 bits each.

My question is why is the address only 6 bits wide? If the address is used to assign values to each memory unit doesn't that mean there is only 6 addresses and 64 memory units?

Thanks for the help!

Here is the HDL code:

module sp_memory( data, addr, we, clk, out );
input [7:0] data;
input [5:0] addr;   
input we;           // Write enable, 1 is write 0 is read;
input clk;

output [7:0] out;

reg [7:0] ram [63:0];       //8 by 64 bit RAM
reg [7:0] addr_reg;

//<statements>
 
 always @ (posedge clk)
 begin
  if(we)
   ram[addr]<=data;
  else
   addr_reg<=addr;
   
 end
 assign out = ram[addr_reg];
 
endmodule

Here is the testbench code:

`timescale 1ns/100ps

module sp_memory_tb;

parameter SYSCLK_PERIOD = 20;// 50MHZ

reg [7:0] data_1;
reg [5:0] addr_1;   
reg we_1;           
reg clk_1;

wire [7:0] out_1;

initial
begin
    clk_1 = 1'b0;
// start write
    
    data_1 = 8'd04;
    addr_1 = 6'd0;  //address 0
    we_1 = 1'b1;    // write mode initialized 
    # 20;
    
    data_1 = 8'd02;
    addr_1 = 6'd1;  //address 1
    # 20;
    
    data_1 = 8'd03;
    addr_1 = 6'd2;  //address 2
    # 20;
    
    data_1 = 8'd11;
    addr_1 = 6'd3;  //address 3
    # 20;
    
    data_1 = 8'd12;
    addr_1 = 6'd4;  //address 4
    # 20;
    
    data_1 = 8'd13;
    addr_1 = 6'd5;  //address 5
    # 20;
    
// start read
   
    addr_1 = 6'd0;  //address 0
    we_1 = 1'b0;    // read mode initialized 
    # 20;
    
    addr_1 = 6'd1;  //address 1
    # 20;
    
    addr_1 = 6'd2;  //address 2
    # 20;
    
    addr_1 = 6'd3;  //address 3
    # 20;
    
    addr_1 = 6'd4;  //address 4
    # 20;
    
    addr_1 = 6'd5;  //address 5
    # 20;
    $stop;
end

//////////////////////////////////////////////////////////////////////
// Clock Driver
//////////////////////////////////////////////////////////////////////
always 
    #5 clk_1 = ~clk_1;


//////////////////////////////////////////////////////////////////////
// Instantiate Unit Under Test:  sp_memory
//////////////////////////////////////////////////////////////////////
sp_memory sp_memory_0 (
    // Inputs
    .data(data_1),
    .addr(addr_1),
    .we(we_1),
    .clk(clk_1),

    // Outputs
    .out(out_1)

);

endmodule
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1
  • \$\begingroup\$ Quick question : what is 2^6? \$\endgroup\$
    – user16324
    Oct 19, 2020 at 13:30

1 Answer 1

2
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ram contains 64 memory units, so addr ranges from 0 to 63. A 6-bit wide signal is enough to hold a number from 0 to 63. From ram[addr]<=data; and assign out = ram[addr_reg];, you can see addr represents a binary number. It's not meant to be used as 6 individual signals.

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3
  • \$\begingroup\$ So you are saying that addr is not part of the memory block, it is just used to assign numbers to the memory units itself ? If that is true, how would I assign a value to the first memory unit, second memory unit etc. I was under the impression that in the test bench the code that said data_1 = 8'd04; and addr_1 = 6'd0; we were assigning the first memory unit a value of 4, \$\endgroup\$
    – yer
    Oct 19, 2020 at 2:27
  • \$\begingroup\$ @yer addr is a number. If you're using SRAM, there's address decoder inside SRAM that will select one word (1 word = 8 bits in your case). Since your ram is implemented by flip-flops, the synthesizer will insert address decoder for you. If addr = 0, you're accessing the 1st unit ram[0]. If addr = 63, you're accessing the last unit ram[63]. etc. Your testbench is actually done this way: ... addr_1 = 6'd0; ... addr_1 = 6'd1; ... addr_1 = 6'd2; .... \$\endgroup\$
    – Light
    Oct 19, 2020 at 2:37
  • \$\begingroup\$ @yer Or think about a C array char ram[64]. A 6-bit wide index can access every element. \$\endgroup\$
    – Light
    Oct 19, 2020 at 2:50

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