SDR over DDR memory in FPGA based design

Question

I am designing a new project which demands the usage of DRAM. I have never interfaced with one before, so my knowledge is rather limited. By analyzing the requirements, it would be sufficient to go with a 128 Mbit capacity running at 100 MHz with a 16 bit transfer per cycle.

By doing the research, I concluded that a SDR DRAM should be my choice for the following reasons:

• The controller is simpler to implement (I am aware that there are controllers available and also vendors may provide their own, but I may implement my own for learning purposes)
• It is good entry level for DRAM
• It does not need dedicated FPGA pins, so more flexibility
• The PCB layout is simpler due to the single ended, 50 Ohm impedance traces, versus the differential of the DDR
• A 16-bit SDR bus has the same number of traces as the 8 bit DDR, so no saving on this
• It uses 3.3V so I don't have to mess with different voltages on the banks (vs the SSTL of DDR)
• A SDR is cheaper than DDR
• Power consumption is lower in DDR, but the SDR consumption is not prohibitive or excessive

Now, based on the above, is there a major reason which I am not aware and have not considered that I should prefer going with DDR instead?

Answer 1

This seems like an XY problem.

Nevertheless, I'll answer:

• DDR DRAM part types are more available (SDR is becoming / has become obsolete)
• SDR is not cheaper. Not on a per-bit or per-device basis. It's considered specialty now.
• You still need to route carefully for timing reasons, be it SDR or DDR
• DDR uses source-sync timing which is much easier to meet. SDR uses system-sync, which faces skew problems
• Lower power (DDR is made on smaller device nodes than SDR)
• Available reference designs (Zynq, etc.) use DDR.

As far as the I/O voltage, it's not such a big deal to place the DRAM pins on the appropriate banks (e.g., 1.8V for DDR2) and power them separately. Suitable DCDC regulator ICs for this are very cheap (1-2A, less than 10 cents in volume).

And differential routing should not be a stumbling block. This only affects DQS and CLK. That's two pairs. In return you get better timing.