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Please consider the following efficiency graphs of the exemplary MP2384 buck sync converter:

enter image description here

What I am trying to understand is why is the efficiency at light loads worse for the cases in which the VIN value is a lot higher than the VOUT. In the end, the efficiency difference is negligible for higher loads. This behavior I have observed for different buck converters in the past as well. I would appreciate all feedback regarding this case.

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The part of the chip that does the management (the comparator, the voltage reference, the PWM generator and various low-level interface circuits) take some amount of current i.e. they are not self-powering and that's basically the main clue. They require current and that current/power quite often is provided by a low-level LINEAR regulator.

Given that the efficiency of that (or any) linear regulator worsens proportional to input voltage, then that linearly regulated power eats into the overall efficiency of the full converter and, it's more obvious at higher input voltages and lower output load powers.

Here's what the quiescent power required by the converter is at various input voltages: -

enter image description here

So, when Vin = 19 volts, the device is "wasting" 2.2 mW and, given that in your 3.3 volt efficiency diagram (on the right) there is a load power of 33 mW at 10 mA load you can begin to see that the "management stuff" is becoming a significant factor. The actual implied losses when producing 10 mA at 3.3 volts will be from the MOSFETs and inductor. They don't come for free either.

So, if I were to add things up, to make an output power of 33 mW at an efficiency of 84% requires a total power in of 39.3 mW. Given that the management stuff consumes about 2.2 mW that leaves about 4 mW wasted in the MOSFETs and inductor.

On a high load power, the 2.2 mW consumed by the management stuff becomes trivial because most of the losses are being created by the MOSFETs and inductor.

For instance, with a 4 amp load and Vout = 3.3 volts, the output power is 13.2 watts. The graph's stated efficiency is 94% hence, the total power is 14.04 watts. In other words 0.84 watts are wasted by MOSFETs and inductor and, it's just not worth trying to factor in the 2.2 mW of the management stuff. But clearly they are significant when you are talking low output powers.

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  • \$\begingroup\$ Thank you for the thorough explanation. While I now understand how is the V_IN relevant, I am still not sure about the fact that efficiency changes with the load. Is it because like you specified because of the losses over the FET's, not the management LDO? \$\endgroup\$ – Łukasz Przeniosło Oct 20 '20 at 9:06
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    \$\begingroup\$ @ŁukaszPrzeniosło efficiency = output power ÷ input power and, if there is very little output power there will still be some input power to keep the management stuff working. Take it to an extreme and say you have zero output power and what do you get: efficiency = zero. \$\endgroup\$ – Andy aka Oct 20 '20 at 9:09
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Besides of the self-consumption mentioned in other answers (that probably dominates loses in a well-designed circuit), there is one more V_IN dependence: switching capacitive loses.

Output switch has internal capacity. It also probably has a snubber. Both of them charge at each switch either to 0 or to V_IN.

These loses are proportional to V_IN squared and mostly independent from the load.

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    \$\begingroup\$ Also, as the duty cycle falls the ratio of the RMS current to the average current in the switching devices and the inductor rises, so your I^2R losses in those parts become larger at lower duty cycles for a given average current. \$\endgroup\$ – Dan Mills Oct 21 '20 at 10:18
  • \$\begingroup\$ @DanMills not sure about the IC in question, but near-idle AC loses in the inductor are more or less manageable. At low enough load it is better to turn off the synchronous rectification and at even less load it well be better to even switch to linear mode. \$\endgroup\$ – fraxinus Oct 23 '20 at 11:36
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The regulator itself consumes current. It has an internal linear LDO to drop input voltage to useful levels. And therefore, LDO losses are higher at higher input voltage, even if the circuitry powered by the LDO uses exactly same amount of power.

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  • \$\begingroup\$ Hi, thank you for the answer. In case the internal LDO consumes the same amount of current over the whole current load range, then I see this chart somehow misleading. Why would the efficiency improve with higher load? \$\endgroup\$ – Łukasz Przeniosło Oct 20 '20 at 8:39
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    \$\begingroup\$ It's the same as if I charge you €0.10 per credit card transaction. It costs €0.10 for a €1 transaction (10%) and it costs €0.10 for a €1000 transaction (0.1%). It is more cost efficient at high transaction rates. \$\endgroup\$ – Transistor Oct 20 '20 at 8:53
  • \$\begingroup\$ No, not the LDO but the circuitry it powers consumes constant power or constant current, so constant current goes into LDO, and LDO has to waste more power as heat with higher input voltage. Imagine that regulator consumes 1mA always. Efficiency is low because if x amount of power is used by the regulator to convert x amount of power to load then efficiency is 50%. But if regulator uses x amount of power to convert 99x amount of power to load, then efficiency is 99%. \$\endgroup\$ – Justme Oct 20 '20 at 8:57
  • \$\begingroup\$ So do I understand correctly that the efficiency graph is simply misleading? The constant, consumed power should not be added to it, because one can think it affects the efficiency, while it does not- its simply always there, no matter what the load is (for VIN amplitude that's ok). \$\endgroup\$ – Łukasz Przeniosło Oct 20 '20 at 9:03
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    \$\begingroup\$ No, it is not misleading. If the regulator needs to output x amount of power out to a load, it requires input power of y, and the x/y is the efficiency for the conversion, including all losses to make the conversion. \$\endgroup\$ – Justme Oct 20 '20 at 9:09
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As the others explained, the regulator draws some current from the input in order to function. This will be current to power internal circuitry plus a variable current to charge the FET gates that is roughly proportional to switching frequency. Let's call this total quiescent current Io.

Since the internal LDO wastes excess voltage as heat, it'll use a power of Io*Vin. Relative to varying output power this management overhead results in lower efficiency at low loads and high Vin.

Switching regulators marketed as "high efficiency at light load" will have some kind of sleep/burst modes or cycle-skipping to reduce these losses. At light load, the chip sleeps, then only resumes switching when the output voltage falls below a threshold, then it tops up the output capacitor with a burst of switching until it reaches another threshold, and goes back to sleep. This reduces Io at the cost of increased output voltage ripple.

If the regulator has a pin that sounds like "Internal VCC" then you can power its internal circuitry and MOSFET driver from another supply, or from the output of the regulator via a diode if the voltage is suitable, which turns off the internal LDO and avoids its losses. This makes it more efficient. If you have two supply voltages, say a small switcher and a high current switcher then you can also power the big switcher's InternalVCC from the small one if voltages are compatible. This optimizes away LDO losses.

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