I am trying to implement a half bridge topology as shown in the figure below: enter image description here

I have replaced the IRF450 with STGW40H60DLFB IGBT.

I have also replaced the 11DF4 with UF4007.

My LTSPICE schematic looks like: enter image description here

My VDS and VGS in the high side and low side is: enter image description here

When I run my LTSPICE simulation with a pulse with 100K frequency, I get: enter image description here

I can't spot a error in my LTSPICE, please let me know if you have any idea what it might be.

MODEL Used for UF4007:

.MODEL UF4007 D N=3.97671 IS=3.28772u RS=0.149734 EG=1.11 XTI=3 CJO=2.92655E-011 VJ=0.851862 M=0.334552 FC=0.5 TT=1.84973E-007 BV=1000 IBV=0.2 Iave=1 Vpk=1000 type=silicon

Spice Model for IR2100 was downloaded from: https://www.infineon.com/cms/en/product/power/gate-driver-ics/ir2110/

Spice Model for STGW40H60DLFB was downloaded from: https://www.digikey.be/product-detail/en/stmicroelectronics/STGW40H60DLFB/497-14364-ND/4696260

  • 1
    \$\begingroup\$ Can you post the contents of the IR2110 subcircuit? It requires registration. You could to also post the contents of the .asc file, it would help. Use ``` as delimiters for the block of text. \$\endgroup\$ Commented Oct 22, 2020 at 8:45
  • \$\begingroup\$ No need for that, anymore. The problem is with your IGBT symbols, see the answer. It's safe to delete your comments. \$\endgroup\$ Commented Oct 22, 2020 at 9:11
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    \$\begingroup\$ I built the circuit using a FET and got the desired results, I will do further research on the circuit using the STGW40H60DLFB and mark your answer as correct. Thanks for your help. \$\endgroup\$ Commented Oct 22, 2020 at 21:52

2 Answers 2


It looks like you used an autogenerated symbol for your IGBT, but you connected it wrong, because the order of the pins is D-G-S. But, instead of using an autogenerated symbol you can make things easier for you if you choose the [Misc]/nigbt symbol, which you can use directly as an IGBT. All you have to do is rename NIGBT with STGW40H60DLFB-V2, and you're done.

You still have to add the correct prefix (right-click on the symbol, change Z to X), I thought that would be implied.

Anyway, the IGBT subcircuit is full of behavioural expressions and it's not very convergence-friendly. I don't know if it will help with your particular schematic, but I poked around and managed to get it working in a simple test by making these changes inside the STGW40H60DLFB-V2.lib file:

  • on line 70 change r_escusione 1z a1 500 to c_escusione 1z a1 10p Rpar=500
  • on line 73 change r_conv1 1y a1 10 to c_conv1 1y a1 10p Rpar=10
  • on line 114 there's a Grg1 ...; add this line, crg1 g2 g 10p rpar=1g right below it
  • on line 168 add a ; at the beginning of the line, in front of E2 ..., then add these two lines below:
g2 50 40 g d1k 1k
r2 50 40 1m
  • on line 204 add a ; at the beginning of the line, in front of E22 ..., and add these two lines below:
G22 502 402 ss d1k 1k
r22 502 402 1m

You can help in your schematic by setting Rser=10...100m for the voltage sources (V3, V4, and V1; V2 can be ignored), adding Rser=1...10m to capacitors (all four), and adding Rpar=10...100k to the inductor. Also try changing V2, A1 and their connections like this:

  • delete A1 and all the connections to the input pins HIN and LIN. V2 should be just sitting there in the schematic with no connections.
  • add [Digital]/buf (not buf1) and connect its input to V2 and its outputs to HIN and LIN pins. There should be a new A1 in the schematic.
  • add vhigh=6 tau=10n tripdt=30n to the new A1.

These changes could help, too:

  • add Vp=0.3 to the .model UF4007 card
  • add this model for the 1N4148:
.model 1N4148 D(Is=2.52n Rs=.568 N=1.752 Cjo=4p M=.4 tt=20n Iave=200m Vpk=75 Vp=0.3 mfg=OnSemi type=silicon)

Try running your schematic with these changes. If you're religious, praying might help.


The suggestion above was correct. The problem was with my IGBTs. I tried to use the STGW40H60DLFB-V2 by choosing the [Misc]/nigbt symbol as suggested above but I couldn't get it to work. So, I used a FET model which can withstand high voltage and the circuit worked. The simulation served its purpose. The correct simulation looks like: enter image description here

The results from the simulation looks like: enter image description here

V(n008) is the input PWN signal to HIN pin. V(n0011) is the inverted input PWN signal to LOW pin. V(n003) is the Drain-Source Voltage of the HIGH side. V(n003,n004) is the Gate-Source Voltage of the HIGH side. V(n004) is the Drain-Source Voltage of the LOW side. V(n0010) is the Gate-Source Voltage of the HIGH side.

In order to simulate this circuit properly without getting errors, the settings in the Tools\ControlPanel\SPICE has to be changed as: enter image description here

  • \$\begingroup\$ I've updated my answer, see if it helps. \$\endgroup\$ Commented Oct 23, 2020 at 7:39

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