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I found the edaplayground website where it seems you can use a variety of tools (if you know the command line options) to test your code. Moderate success so far, but when trying Cadence Xcelium 19.09 (the example counter from another thread) it is barfing on the if statement conditional saying...

xrun: 19.09-s012: (c) Copyright 1995-2020 Cadence Design Systems, Inc.
      if (Cnt_En OR not Carry_Out_a) then
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xmvhdl_p: *E,OPTYMM (testbench.vhd,37|18): operator argument type mismatch 87[4.3.3.2] 93[4.3.2.2] [7.2] [10.5].
      if (Cnt_En OR not Carry_Out_a) then
                  |
xmvhdl_p: *E,IMPCOP (testbench.vhd,37|18): Indicated Expression could not be converted to expression of type BOOLEAN using Implicit Condition Operator ?? LRM2008 [9.2.9].

Cnt_En and Carry_Out_a are both std_logic, one an input and the other an output. NOT and OR are defined for both types and should produce a compatible type (seems it actually returns a UX01 subtype of std_ulogic) which can then be converted to BOOLEAN.

Once again this is working in several tools. Is Cadence being overly picky or is this really an error that other tools are ignoring.

Then the really important question, why do I keep finding all these issues???

Oh, then the other thing I might point out is it's possible what it's really saying is that it is NOT using VHDL-2008. Anyone know the command line argument for the various tools to enable VHDL-2008 in Cadence Xcelium? The Synopsys tool clearly needs VHDL2008 enabled and I can't find the command line option for that either. Seems looking for the manuals exposes you to web sites that want to infect your computer.

The Aldec Riviera Pro tool unsurprisingly errors out in simulation rather than compile... the EPWAVE tool doesn't understand and complains there is only one "slice" of data. ghdl won't take the VHDL-2008 command line option I found "--std=08". Only the Mentor Questa 2020.1 tool happily compiles and runs the simulation with the expected happy results.

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    \$\begingroup\$ Yeah this is specifically allowed from VHDL-2008 on. If Gadence is 12 years behind the times, sometimes it's just not worth the hassle : just write if (Cnt_En OR not Carry_Out_a) = '1' and move on. GHDL should accept that option after the command, e.g. ghdl -a --std=08 VHDL_test.vhd ... unless you're using a REALLY old release. Then update from github.com/ghdl \$\endgroup\$ – Brian Drummond Oct 24 at 20:20
  • \$\begingroup\$ Don't really need the fix you suggest. As I compared the entity port entries to the instantiation of the Gowin tool, there is no WE. if (Wr_CE) works fine, so the condition operator is not the issue. The i/Os actually makes some sense since one port is read and the other write. Gowin compiles it until it reports the error of running out of FFs in the 9 kLUT device. lol \$\endgroup\$ – gnuarm Oct 25 at 6:50
  • \$\begingroup\$ I think the tools at EDAPlayground are pretty current. Finally got ghdl to work a bit. Turned on VHDL-2008 and most stuff is working. But it doesn't know what to_hstring is. That's supposed to be part of std_logic_1164 now. How can that not be found? Guess ghdl hasn't caught up with a 12 year old standard??? \$\endgroup\$ – gnuarm Oct 25 at 6:52
  • \$\begingroup\$ to_hstring works here ... GHDL 1.0-dev (v0.37.0-1065-g6bf4e741) updated after your earlier testcase. As does my earlier version, GHDL 0.36-dev (v0.35-153-gba14e9da). I wonder when EDA Playground last updated, or if they have mis-installed the libraries? It SAYS 0.37 so to_hstring should work. Could you add a minimal reproducer or ask a new question so I can look into this some? \$\endgroup\$ – Brian Drummond Oct 25 at 12:47
  • \$\begingroup\$ My code is shown in the thread on the integer_vector. In EDA_Playground the two entities have to be split off and posted separately as design and testbench or ghdl gets upset with an empty file and I can't figure out how to tell the tool not to use one of the files. \$\endgroup\$ – gnuarm Oct 25 at 23:33

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