I found the edaplayground website where it seems you can use a variety of tools (if you know the command line options) to test your code. Moderate success so far, but when trying Cadence Xcelium 19.09 (the example counter from another thread) it is barfing on the if statement conditional saying...
xrun: 19.09-s012: (c) Copyright 1995-2020 Cadence Design Systems, Inc. if (Cnt_En OR not Carry_Out_a) then | xmvhdl_p: *E,OPTYMM (testbench.vhd,37|18): operator argument type mismatch 87[126.96.36.199] 93[188.8.131.52] [7.2] [10.5]. if (Cnt_En OR not Carry_Out_a) then | xmvhdl_p: *E,IMPCOP (testbench.vhd,37|18): Indicated Expression could not be converted to expression of type BOOLEAN using Implicit Condition Operator ?? LRM2008 [9.2.9].
Cnt_En and Carry_Out_a are both std_logic, one an input and the other an output. NOT and OR are defined for both types and should produce a compatible type (seems it actually returns a UX01 subtype of std_ulogic) which can then be converted to BOOLEAN.
Once again this is working in several tools. Is Cadence being overly picky or is this really an error that other tools are ignoring.
Then the really important question, why do I keep finding all these issues???
Oh, then the other thing I might point out is it's possible what it's really saying is that it is NOT using VHDL-2008. Anyone know the command line argument for the various tools to enable VHDL-2008 in Cadence Xcelium? The Synopsys tool clearly needs VHDL2008 enabled and I can't find the command line option for that either. Seems looking for the manuals exposes you to web sites that want to infect your computer.
The Aldec Riviera Pro tool unsurprisingly errors out in simulation rather than compile... the EPWAVE tool doesn't understand and complains there is only one "slice" of data. ghdl won't take the VHDL-2008 command line option I found "--std=08". Only the Mentor Questa 2020.1 tool happily compiles and runs the simulation with the expected happy results.