# Where can I connect the unused input to preserve the logic expression?

So there is an unused input for the bottom NAND gate (even though it is not shown in the picture) and the question wants us to connect it while preserving the logic expression. I know when we connect it to the ground, the lower NAND gate never outputs 0. So I assume we are not going to connect it to the ground. But when we connect it to the +5V supply or E, we can get 0 or 1 as an output. Connecting it to E makes it work like it is a two-input NAND gate. I know I have to choose one of them but which one. I would appreciate it if I can get an explanation of what I should do when I come across these kinds of problems.

By the way I assumed we needed to connect it to E and made these answers (I would appreciate feedback to these also):

## TRUTH TABLE

For the truth table I used this logic expression:
!((A&B)&(C&D)&(!(D&E)))

• If the inputs signals are rapidly changing and have a non-zero source impedance then connecting two inputs together produces more loading capacitance blah blah.... Oct 25, 2020 at 11:06
• Maybe you need to choose a single solution, but 2. and 3. are both right. Oct 25, 2020 at 11:13
• What are the cases where the logic expression will not be preserved? Is it only dependent on the ouput? For example when you get 0 or 1 it is preserved, but when you only get 1 it is not preserved? Oct 25, 2020 at 11:25

when we connect it to the +5V supply or E, we can get 0 or 1 as an output. Connecting it to E makes it work like it is a two-input NAND gate. I know I have to choose one of them but which one.

You could do it either way and the logic would work the same. So why choose one over the other?

1. With 2 inputs connected together the signal loading is increased. This could be a problem if the signal driver is close to its fan-out limit.

2. Unused inputs wired to Ground or V+ should take a short route directly to the IC's own supply pin, to avoid possible EMI and supply voltage differences. Many ICs have an input voltage limit of ~0.3V above and below the supply lines, which can easily occur on large boards with high current draw. If the IC is in a socket or breadboard then the supply pin might accidentally become disconnected, causing the IC to draw full supply current through the unused input's protection diode.

3. Connecting adjacent pins usually makes PCB routing easier. In your case you have the obvious choice of connecting pin 13 to pin 14 for logic high and using pins 1 and 2 for inputs, or doing it according to your wiring diagram. Until you route the PCB you won't know which one is more convenient.

In more complex circuits with dense layouts it is quite common to see signals routed to different pins than expected. For example a data bus might be wired 'randomly' to a bus buffer or RAM chip because it doesn't care which bit is which. PCB layout programs often have 'pin-swap' and 'gate-swap' functions which allow the PCB designer to easily optimize the layout.

• Thank you for your answer. Also, what are the cases where the logic expression will not be preserved? Does it only depend on the output? For example when you get 0 or 1 it is preserved, but when you only get 1 it is not preserved? Also, when trying to find if it is preserved or not, should we look at the whole circuit or just the gate where the problem is? In genereal, how can we tell what breaks the logic expression? Oct 25, 2020 at 15:50
• It will not be preserved in cases where the 'unused' input needs to have a fixed logic level to ensure correct output, eg. in an Exclusive OR gate, or (momentarily) where different gate delays could cause unacceptable glitching on the output. In the case of TTL (N)AND and (NO)OR gates it's fine because all inputs need to be high or low to change the output, and they all go to a common point inside the IC (eg. multiple Emitters on a single transistor) with equal delays. You can tell if the logic is 'broken' using the usual techniques (eg. Karnaugh map). Oct 25, 2020 at 22:21
• My friends are saying connecting it to ground is the right way. I know it is not right, which way of thinking could be leading them to this answer? Oct 28, 2020 at 8:23
• Also, can the explanation of my answer be as follows; "Connecting the unused pin to the ground does not preserve the logic since the output of 0 can never occur on that NAND Gate, but connecting it to E or the +5V power supply will preserve the logic since the output of 0 and 1 can be the output of that NAND Gate. Between connecting to E or connecting to the +5V, connecting to +5V makes more sense since connecting two inputs together will increase the signal loading and could be a problem if the signal driver is close to its fan-out limit." ? Oct 28, 2020 at 8:25
• I also looked up what fan-out limit is and found that the number of logic gate inputs that can be driven from the output of a single logic gate is termed as fan out of logic gates. In our case, we have two logic gate inputs driven from E, but E is not an output of a logic gate. Since the definition says it needs to be driven from a logic gate, shouldn't it be the wrong way of explaining this question? Oct 28, 2020 at 8:33