Problem: A simple current mirror is set up with two NPN transistors. \$V_{CC}=12\$ Volts \$+V_{in}= 30\$ Volts. Load resistance \$R_L\ =\ 1\ K\Omega \$.

What is the resistance value interval for output transistor to stay in forward-active region and not to be deformed?

( \$V_{BE}=0.7\ V, V_{CE,SAT}=0.6\ V,\ V_{CE,MAX}=25\ V, I_0=I_R\$)


simulate this circuit – Schematic created using CircuitLab

What I have tried so far:

$$ I_{R} = \dfrac{V_{CC}-V_{BE}}{R} $$

$$ I_{R}=I_C+\dfrac{2I_C}{\beta}=I_C \Big(1+\dfrac{2}{\beta}\Big) $$ $$ \therefore I_0=I_C=I_R \times \dfrac{1}{1 + \frac{2}{\beta}} $$

$$ I_0 = I_C = \dfrac{V_{CC}-0.7}{R}\times \dfrac{1}{1+\frac{2}{\beta}}$$

but I am stuck here since \$\beta\$ value is unkown could not take it further.

PS: I am not asking for a full solution.

  • 1
    \$\begingroup\$ Why not show a schematic?you can probably neglect the beta value as it is insignificant compare the the assumptions for Vbe and Vce(sat) \$\endgroup\$ Oct 25, 2020 at 18:55
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    \$\begingroup\$ Assumptions for Vbe=0.7 vs 0.65 or 0.6V @ Ic=1mA which is most accurate means possible 10% error with result affected by 0.1/12V or ~@% while beta= 150 +/-50% typ. with 1+2/beta affects result around 2%.. just use Ohms Law for the Vcc drop unless you wish to use data sheets \$\endgroup\$ Oct 25, 2020 at 19:06
  • \$\begingroup\$ Added a schematic. Thank you I will try to take it further. \$\endgroup\$
    – Nabla
    Oct 25, 2020 at 19:07
  • 1
    \$\begingroup\$ You missed a link in the schematic. \$\endgroup\$
    – fraxinus
    Oct 25, 2020 at 19:15
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    \$\begingroup\$ You're overthinking this. In parentheses it tells you the max and minimum voltages across Q2. Use them to find voltages across RL, then find values of IO. Now you can see the voltage across R, and you know the range of IR, so go to it. \$\endgroup\$
    – user16324
    Oct 25, 2020 at 19:43

2 Answers 2


Your question is about the so-called "compliance voltage" - a very important property of current sources (despite the respectful name "current mirror", here Q2 is just a simple transistor current source... or, more correctly, a sink).

When you begin increasing RL, the voltage drop VRL across it will begin increasing as well. To compensate this increase, Q2 will begin decreasing its collector voltage with the same rate. Figuratively speaking, you can think of the Q2 collector-emitter part as of a variable (dynamic) "resistor" that complements the RL resistance to a constant value; hence the constant output current.

Finally, the Q2's Vc will reach VCEsat = 0.6 V. This will happen when VRL = +Vin - 0.6 V and, as they say, Q2 becomes saturated.

After that, the "magic" of Q2 constant-current source ceases. It cannot decrease its "resistance" anymore... and the current will begin decreasing (according to Ohm's law) when you continue increasing RL.


Expert comments.

i.e. not an answer

Saturation depends alot on Ic due to bulk Rce, so when using mismatched and/or unknown hFE with 50% tolerance typ. Finding the exact value for Vce(sat) may vary widely (10%) easily.

Also Vce(sat) is not a perfect switch and hFE will drop to about 10% of hFE max for rated Ic/Ib=10 @ Ic= TBD current in specs.

So best case is just use the Vcc1/R1 =Vcc2/R2 That yields R1=400 but for 0.6=Vce around 380 then lower with low hFE power transistors.

and let Vce(sat)=Vbe as hFE can “start” saturation (reduction in hFE) @ Vce =1 to 2V at rated currents due to unspecified Rce=Vce(sat)/Ic effects on hFE.


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