RC pulldown on the MDI lines between the ethernet PHY and RJ45 Connector

Question

I came across this circuit as part of the Xilinx Spartan 6 601 evaluation kit board diagram:

Left hand IC is an 88E1111 (incidentally, the datasheet of which is incredibly difficult to obtain), the lines require 100 Ohm differential impedance, which explains the 47 Ohm resistors (why not 49.9 1% tolerance resistors that I've seen in the same scenario on other boards?).

I think I understand what is happening: the voltage divider centre is supposed to sit at zero, but if the diff lines aren't 100% inverted relative to each other, say during a transition from low to high, then the centre of the divider will be non zero and the cap will smooth that change. Is this right? And if so, doesn't the RC filtering have an affect on the transmission lines and rates themselves?

Also, what kinds of voltages are on these lines? 47 ohm isn't very big, so won't there be some current flow through the resistors, in the order of mA? On second thought, the current probably isn't too significant.

Answer 1

This setup allows for a 100 ohm differential termination and a 50 ohm termination at higher frequencies for the ustrip/strip lines that the differential traces will likely be laid out with. the net DC term across the differential traces will not be zero but will be midrail.

The differential amplifiers inside the IC all have CMFB (common mode feedback) amplifiers so the capacitors help hold this value and stabilize the DC value, they would of course need to be designed with these caps in mind but the 47 ohms does help ensure the phase margin is met.

The draw back of course is that there is now a RC time constant associated with the CMFB and the common mode level.

It is likely that these measures all help ensure a larger eye opening.