# Why are the mosfet gate tunneling currents disappearing in a bsim4 simulation under a width and/or length of 10µm? (TSMC65)

I am trying to simulate the current from the gate of a mosfet to its body (drain, source and bulk are shorted). But with a downscaling of the transistor the current disappears abruptly and fully under 10µm, although the igcmod and igbmod flags are set to 1 in the model (tunnel current simulation is on). The purpuse of this is the design of a floating gate memory cell in standard TSMC65 process; something like this.

I tried remodeling the behaviour in an external element, defined by a verilogA file which contains all the necessary formulas from the BSIM4 documentation, but the resulting current (above 10µm) doesn't match the original simulation. While reading through the technology parameters i noticed though that single transistor models are defined multiple times, usually prefaced with something like "1:ptype ..." then again "2:ptype" and so on. Could my problem have something to do with the simulator using different models of the transistor for different voltages or sizes? And how can I make sure the tunneling current will be calculated at all times?