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I am trying to simulate the current from the gate of a mosfet to its body (drain, source and bulk are shorted). But with a downscaling of the transistor the current disappears abruptly and fully under 10µm, although the igcmod and igbmod flags are set to 1 in the model (tunnel current simulation is on). The purpuse of this is the design of a floating gate memory cell in standard TSMC65 process; something like this.

I tried remodeling the behaviour in an external element, defined by a verilogA file which contains all the necessary formulas from the BSIM4 documentation, but the resulting current (above 10µm) doesn't match the original simulation. While reading through the technology parameters i noticed though that single transistor models are defined multiple times, usually prefaced with something like "1:ptype ..." then again "2:ptype" and so on. Could my problem have something to do with the simulator using different models of the transistor for different voltages or sizes? And how can I make sure the tunneling current will be calculated at all times?

Thank you in advance!

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  • \$\begingroup\$ The fact that you see unexpected / abrupt behavior immediately alerts me that this behavior is very likely not modeled properly. How a model behaves depends on the model itself (BSIM4) but also the model parameters that are provides by the manufacturer (TSMC). The normal procedure is that MOSFETs are fabricated, then measured and from those results, model parameters are extracted. Maybe the gate tunneling was not measured so the parameters aren't reliable resulting in unreliable simulation results. I would contact TSMC modeling support and discuss the issue with them. \$\endgroup\$ – Bimpelrekkie Oct 27 '20 at 9:05

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