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I am hardware design engineer. I had seen lot of board designs since 2015. In my career I have seen that most of the RESET signals are of active low signals. Is there any logical reason behind that?

Following are the major reset signals which will be present in the most of embedded systems

  1. Power on Reset
  2. Cold Reset
  3. Warm Reset
  4. PCIe Reset
  5. DDR Reset
  6. USB PHY reset
  7. SPI protocol Chip select

Any insight would be greatly appreciated.

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The /reset pin on most MCUs is an I/O pin, so it has two functions:

  • allowing an external reset command to the MCU, and
  • letting the outside know that the MCU is live and operational

Pulling the line low to indicate that the part is alive isn't a great idea, because then how would you distinguish that from loss of power?

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This EE.SE post clearly answers your question.

Plus, I think this is also a tradition. In the past when the flip-flops are made from only NAND gates (I don't know if today it's been done in the same way), making the RESET signal active-low was easier.

enter image description here Fig1: D Flip Flop /w RESET built with only NAND gates (Img Src)

enter image description here Fig2: SR Flip Flop /w CLEAR built with only NAND gates (Img Src)

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  • \$\begingroup\$ Thanks @Rohat Kılıç , Latest technology has been migrated CMOS logic right? It should support push pull logic also.. which is the efficient one. \$\endgroup\$ Oct 30 '20 at 7:00
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    \$\begingroup\$ EE.SE question electronics.stackexchange.com/questions/60401/… also bears on the subject; pay attention the accepted answer mentioning wired-OR logic consideration \$\endgroup\$
    – V.V.T
    Oct 30 '20 at 7:39

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