I am attempting to perform a CDC from a FIFO Generator IP to AXI registers. Forgive my lack of understanding of Verilog, I'm a VHDL guy.
What I have:
cdc_fifo_64 timer_fifo(
.rst(reset_p), // active high
.wr_clk(CNTR_CLK), // MUST be 500MHz
.rd_clk(S_AXI_ACLK), // MUST be 100MHz
.din(timer),
.wr_en(TRIGGER_os),
.rd_en(1'b1),
.dout(timer_cdc),
.full(),
.empty()
);
cdc_fifo_32 interval_fifo(
.rst(reset_p), // active high
.wr_clk(CNTR_CLK), // MUST be 500MHz
.rd_clk(S_AXI_ACLK), // MUST be 100MHz
.din(interval),
.wr_en(TRIGGER_os),
.rd_en(1'b1),
.dout(interval_cdc),
.full(),
.empty()
);
always @(S_AXI_ACLK) begin
slv_reg2 <= interval_cdc;
slv_reg1 <= timer_cdc[63:32];
slv_reg0 <= timer_cdc[31:0];
end
I do not want the last block to add a clock cycle of delay for something as simple as renaming signals.
In VHDL I could simply assign bit fields (so I could use slv_reg1 <= timer_cdc(63 downto 32)) and have no issues with sequential/combinatorial assignments. But here, I have reg signals (and I should not be changing slv_regX to a wire or renaming it). How can I assign these so that I simply rename the reg output to a bit field of another reg?
slr_reg1 <= timer_cdc[63:32]
does, in fact, directly latch the 32nd to 63rd bit oftimer_cdc
intoslv_reg1
, exactly as you want it. \$\endgroup\$<=
) in a process (always @...
)? \$\endgroup\$.dout[63:32](slv_reg1)
. For your second comment, I am doing that because doingassign slv_reg* =
doesn't work for a reg signal, right? \$\endgroup\$