"Renaming" an output reg to another reg?

Question

I am attempting to perform a CDC from a FIFO Generator IP to AXI registers. Forgive my lack of understanding of Verilog, I'm a VHDL guy.

What I have:

cdc_fifo_64 timer_fifo(
   .rst(reset_p), // active high
   .wr_clk(CNTR_CLK), // MUST be 500MHz
   .rd_clk(S_AXI_ACLK), // MUST be 100MHz
   .din(timer),
   .wr_en(TRIGGER_os),
   .rd_en(1'b1),
   .dout(timer_cdc),
   .full(),
   .empty()
);
  
cdc_fifo_32 interval_fifo(
  .rst(reset_p), // active high
  .wr_clk(CNTR_CLK), // MUST be 500MHz
  .rd_clk(S_AXI_ACLK), // MUST be 100MHz
  .din(interval),
  .wr_en(TRIGGER_os),
  .rd_en(1'b1),
  .dout(interval_cdc),
  .full(),
  .empty()
);
  
always @(S_AXI_ACLK) begin
  slv_reg2  <= interval_cdc;
  slv_reg1  <= timer_cdc[63:32];
  slv_reg0  <= timer_cdc[31:0];
end

I do not want the last block to add a clock cycle of delay for something as simple as renaming signals.

In VHDL I could simply assign bit fields (so I could use slv_reg1 <= timer_cdc(63 downto 32)) and have no issues with sequential/combinatorial assignments. But here, I have reg signals (and I should not be changing slv_regX to a wire or renaming it). How can I assign these so that I simply rename the reg output to a bit field of another reg?

Answer 1

You can use continuous assignment instead of procedural assignment.

For example

wire slv_reg2;

// ...

assign slv_reg2 = interval_cdc;

I should not be changing slv_regX to a wire or renaming it

You should. Declaring a signal as wire or reg in Verilog has nothing to do with whether the signal is actually the output of a register or of combinatorial logic. It has nothing to do with whether registers or combinatorial logic is synthesized. It only determines how you can use that signal name in the Verilog language.

You can assign to wire signals by connecting them to submodule instance outputs, or with continuous assignment statements (assign). You can assign to reg signals in procedural blocks. When writing Verilog, you simply have to get used to changing the signal declaration between reg and wire if you change how you assign to the signal within the Verilog code. Again, this will have very little to do with what logic (combinatorial or sequential) gets inferred when you synthesize your design.

SystemVerilog allows you to avoid this confusing mess (at least if you don't need multiply-driven signals, such as wired-or signals) by allowing you to declare a signal as logic. This allows it to be assigned to in either a procedural or continuous assignment. Some Verilog tools may also allow using the logic signal type.

Some simulation and synthesis tools may also ignore how you declare your signals and allow you to make procedural assignments to wire signals and/or continuous assignments to reg signals, but if you write your code assuming you will be using one of these tools, it is likely to break when you for some reason have to switch to another tool.