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Is it bad coding practice to use Buffer Ports in VHDL?

I define an entity with an out port with o_done.

entity blahblah is
  port (
...other signals...
 o_done    : out std_logic;              
  );
end entity blahblah;

The synthesizer does not like me reading an out port and wont synthesize it - even though it is legal VHDL 2008 code. I can't change my synthesizer.

I use o_done in 2 clocked processes:

process begin
    wait until rising_edge(clk);
    if (reset = '1') then
      o_done <= '0';
    else
      if ( State1 ) then
        o_done <= '1';
      elsif ( o_done = '1' AND State0 ) then
        o_done <= '1';
      else
        o_done <= '0';
      end if;
    end if;
  end process;

  process begin
    wait until rising_edge(clk);
    if (reset = '1') then
      count <= to_unsigned(0, 8);
    else
      if( stateS0 AND done = '1' ) then
        count <= to_unsigned(0, 8);
      elsif( stateS1 AND y_counter >= 2 AND p >= 0 ) then
        count <= count + 1;
      end if;
    end if;
  end process;

Again, o_done, since defined as out in the port declaration, is not synthesizable since the synthesis engine isn't fully VHDL 2008 compatible. I can't change the synthesizer.

So how do I work around o_done being an output port and wanting to read it ?

Can I make an intermediate signal - how do I do this typically ?

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  • \$\begingroup\$ Buffer ports as in GPIO? Or buffering signals? \$\endgroup\$ – Voltage Spike Oct 30 '20 at 17:23
  • \$\begingroup\$ Please show an example code \$\endgroup\$ – Eugene Sh. Oct 30 '20 at 17:35
  • \$\begingroup\$ The question is not clear to the community. You can say why you wanted to use buffer port with a code snippet. \$\endgroup\$ – Mitu Raj Oct 30 '20 at 18:05
  • \$\begingroup\$ I Fixed it now. \$\endgroup\$ – user4434 Oct 30 '20 at 18:27
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Yea, you can use the simple solution of creating an internal signal:

signal done : std_logic ;

Use this signal inside your clocked process.

And simply assign it to o_done as a concurrent statement inside architecture definition:

o_done <= done ;

I haven't really had the need to use buffer ports in VHDL codes till now. This is something I extracted from Xilinx Vivado Synthesis Guide:

VHDL allows buffer port mode when a signal is used both internally, and as an output port when there is only one internal driver. Buffer ports are a potential source of errors during synthesis, and complicate validation of post-synthesis results through simulation. reference: Chapter 5, Xilinx Vivado Synthesis Guide

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  • \$\begingroup\$ Attempted this but the problem is that o_done value and then done value is state so i am not sure how to define done when it is state dependent. \$\endgroup\$ – user4434 Oct 30 '20 at 18:43
  • \$\begingroup\$ Both done and o_done will transit exactly the same. Both are same signals technically on hardware even though with different names. \$\endgroup\$ – Mitu Raj Oct 30 '20 at 18:49
  • 1
    \$\begingroup\$ Okay, I got it to work, thanks. I had to modify the statement for the state dependence. \$\endgroup\$ – user4434 Oct 30 '20 at 18:55
  • \$\begingroup\$ Yea, but his synthesiser doesn't support VHDL-2008. Must be pretty old synthesiser then. \$\endgroup\$ – Mitu Raj Oct 30 '20 at 18:57
  • 1
    \$\begingroup\$ Maybe you are missing some switches. Sometimes you have to manually specify that you want to use VHDL-2008 while compiling. \$\endgroup\$ – Mitu Raj Oct 30 '20 at 18:59

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