# Using Buffer Ports in VHDL?

Is it bad coding practice to use Buffer Ports in VHDL?

I define an entity with an out port with o_done.

entity blahblah is
port (
...other signals...
o_done    : out std_logic;
);
end entity blahblah;


The synthesizer does not like me reading an out port and wont synthesize it - even though it is legal VHDL 2008 code. I can't change my synthesizer.

I use o_done in 2 clocked processes:

process begin
wait until rising_edge(clk);
if (reset = '1') then
o_done <= '0';
else
if ( State1 ) then
o_done <= '1';
elsif ( o_done = '1' AND State0 ) then
o_done <= '1';
else
o_done <= '0';
end if;
end if;
end process;

process begin
wait until rising_edge(clk);
if (reset = '1') then
count <= to_unsigned(0, 8);
else
if( stateS0 AND done = '1' ) then
count <= to_unsigned(0, 8);
elsif( stateS1 AND y_counter >= 2 AND p >= 0 ) then
count <= count + 1;
end if;
end if;
end process;


Again, o_done, since defined as out in the port declaration, is not synthesizable since the synthesis engine isn't fully VHDL 2008 compatible. I can't change the synthesizer.

So how do I work around o_done being an output port and wanting to read it ?

Can I make an intermediate signal - how do I do this typically ?

• Buffer ports as in GPIO? Or buffering signals? – Voltage Spike Oct 30 '20 at 17:23
• Please show an example code – Eugene Sh. Oct 30 '20 at 17:35
• The question is not clear to the community. You can say why you wanted to use buffer port with a code snippet. – Mitu Raj Oct 30 '20 at 18:05
• I Fixed it now. – user4434 Oct 30 '20 at 18:27

Yea, you can use the simple solution of creating an internal signal:

signal done : std_logic ;


Use this signal inside your clocked process.

And simply assign it to o_done as a concurrent statement inside architecture definition:

o_done <= done ;


I haven't really had the need to use buffer ports in VHDL codes till now. This is something I extracted from Xilinx Vivado Synthesis Guide:

VHDL allows buffer port mode when a signal is used both internally, and as an output port when there is only one internal driver. Buffer ports are a potential source of errors during synthesis, and complicate validation of post-synthesis results through simulation. reference: Chapter 5, Xilinx Vivado Synthesis Guide

• Attempted this but the problem is that o_done value and then done value is state so i am not sure how to define done when it is state dependent. – user4434 Oct 30 '20 at 18:43
• Both done and o_done will transit exactly the same. Both are same signals technically on hardware even though with different names. – Mitu Raj Oct 30 '20 at 18:49
• Okay, I got it to work, thanks. I had to modify the statement for the state dependence. – user4434 Oct 30 '20 at 18:55
• Yea, but his synthesiser doesn't support VHDL-2008. Must be pretty old synthesiser then. – Mitu Raj Oct 30 '20 at 18:57
• Maybe you are missing some switches. Sometimes you have to manually specify that you want to use VHDL-2008 while compiling. – Mitu Raj Oct 30 '20 at 18:59