Is it bad coding practice to use Buffer Ports in VHDL?
I define an entity with an out port with o_done.
entity blahblah is port ( ...other signals... o_done : out std_logic; ); end entity blahblah;
The synthesizer does not like me reading an out port and wont synthesize it - even though it is legal VHDL 2008 code. I can't change my synthesizer.
I use o_done in 2 clocked processes:
process begin wait until rising_edge(clk); if (reset = '1') then o_done <= '0'; else if ( State1 ) then o_done <= '1'; elsif ( o_done = '1' AND State0 ) then o_done <= '1'; else o_done <= '0'; end if; end if; end process; process begin wait until rising_edge(clk); if (reset = '1') then count <= to_unsigned(0, 8); else if( stateS0 AND done = '1' ) then count <= to_unsigned(0, 8); elsif( stateS1 AND y_counter >= 2 AND p >= 0 ) then count <= count + 1; end if; end if; end process;
Again, o_done, since defined as out in the port declaration, is not synthesizable since the synthesis engine isn't fully VHDL 2008 compatible. I can't change the synthesizer.
So how do I work around o_done being an output port and wanting to read it ?
Can I make an intermediate signal - how do I do this typically ?