Is there a way to prevent the random state of a shift register when power is applied?

Question

I have a project with two seperate output shift registers and they are working fine. They both have LEDs at the moment but one shift register will eventually be controlling relays and then solenoid valves to control water flow. The issue I have is when I turn the power on, the 8 channels of the shift registers are rarely in the off state. Normally some are on which is no good having the solenoid valves randomly turn on then off when power is turned on. Is there are way I can force the registers to be off when power is applied? The shift registers I am using are both 74HC595N.

EDIT

The green LEDs light up before the MC can initialise the shift register.

Answer 1

The chip you are using has an output enable pin that allow you to keep the shift register outputs in a high impedance state until you shift in known data. You would probably want to use a microcontroller for this.

From NXP Datasheet:

Additionally you can use the master reset pin to clear shift register contents if you want them to be all 0. If you use this method it's probably doable to set up a resistor and capacitor to keep the pin low for a certain duration of time after power up.

Answer 2

You will need to combine three general concepts to obtain what you want in this particular case.

1. A power-on reset function: This circuit element senses the power supply voltage, compares it to an internal threshold, and supplies an output (call it PowerOK) that indicates whether the supply has exceeded the threshold. In most cases, PowerOK is a digital signal. As the supply rises from zero, PowerOK remains low until the supply crosses the threshold, then rises to a logic HIGH and tracks the supply as it completes its rising transient. To be useful, the threshold must be hysteretic, lest the output chatter on its way up or down.
2. A reset function for the digital state elements: On your 74HC595N, this function is supplied by the MRbar pin. Its internal flops have an asynchronous "resetb", where the flop outputs are always some fixed state (either 0 or 1) whenever "resetb" is LOW, i.e., in the Reset state. Why "resetb", and not "reset"? When the supply comes up, you always want to start your digital state elements in a known state. But if the supply voltage is below the minimum, a valid logic LOW is available (ground) but a valid HIGH may not be.
3. Assigning reset values to each element that requires them. Suppose your shift register produces all 0's in the reset state. Suppose further that some elements you're controlling need to 0's, while others need to be 1's. What to do? Generally, the most robust thing to do is to place combinational logic after the state element, and in front of the controlled element.

To glue together these ideas, you'll need to drive your MRbar pin with PowerOK (or possibly, PowerOK AND SomeOtherLogic). Depending on what else in the system uses PowerOK, you may have to generate a locally-delayed copy of it for your shift reg or some other element. Also, depending on the reset value for each element (relay, solenoid, etc.) you may need to add static logic. It may be as simple as an inverter, but you'll need to make sure that the logic function (a) provides the proper reset value when PowerOK rises, and (b) that the logic circuitry can function reliably at your rising PowerOK threshold.

Answer 3

The easiest way that requires very little additional hardware is to drive the OE of the shift register from another GPIO line from the processor.

This GPIO line should be pulled high with a resistor sp that at power-on it is guaranteed to be in the high-state. This will ensure that the output of the shift register is in the high-impedance state.

At power-on the software should initialize the shift register before setting the OE line to a logic low. The OE line can then be left in this state

This sequence will ensure that the LEDs remain off until the software has had a chance to initialize the circuitry.