The SN74LVC1G17 was used on a DIO circuit as a buffer on a FPGA. Is it used to have a higher current on the output ? Here is the datasheet https://www.ti.com/lit/ds/symlink/sn74lvc1g17.pdf?ts=1604252447419

  • \$\begingroup\$ Please edit your question and detail your situation and what you are working on - in considerable detail. \$\endgroup\$
    – TonyM
    Nov 2 '20 at 15:54
  • \$\begingroup\$ Which way it was buffering? Into FPGA, or from FPGA? \$\endgroup\$
    – Justme
    Nov 2 '20 at 16:15
  • \$\begingroup\$ it's typically very rare for general IO to be directly connected to an fpga pin if for no other reason than the io voltage on fpga or at least a modern one is fairly low... Also you have to start considering things like ESD etc. \$\endgroup\$
    – MadHatter
    Nov 2 '20 at 16:51
  • \$\begingroup\$ @Justme the circuit is doing both. \$\endgroup\$
    – Amen0
    Nov 2 '20 at 17:02
  • \$\begingroup\$ @MadHatter Thank you. \$\endgroup\$
    – Amen0
    Nov 2 '20 at 17:02

Yes, the main purpose is to have an output signal wich is more robust than the input signal, expecially when the next circuit is edge-sensitive (i.e. you need very steep edges).

  • 1
    \$\begingroup\$ Thought I would not vote this answer up, I don't understand why it has been voted down. \$\endgroup\$
    – Fredled
    Nov 2 '20 at 21:10

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