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I am designing board which has got 4 DDR3 Die on it, 64 bit SDRAM interface. DDR3 Memory controller will be xilinx FPGA. I have some confusion in the signal routing from the DDR3 interface to DDR3 memory controller. How to decide the routing topology for the 4 DDR3 die? Any logical reason for selecting T topology and flyby topology?

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With 4 endpoints T routing for address + control doesn’t work out so well. Much more straightforward to use fly-by and have Vtt endpoint termination.

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    \$\begingroup\$ I request you to elaborate it sir... Can you explain me the logical reason behind the selection of the topology? \$\endgroup\$
    – Ananthesh
    Commented Nov 3, 2020 at 6:25
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    \$\begingroup\$ Fly-by routing greatly simplifies making multiple-chip connections like DIMMs, as they can be routed in a daisy-chain fashion. The daisy-chain uses end-termination, so each device along the path sees good signal. The side effect - skew - is dealt with in DDR3 which has support for per-lane deskew. \$\endgroup\$ Commented Nov 3, 2020 at 17:13
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    \$\begingroup\$ Your configuration, 4 devices, can take advantage of this DDR3 feature and have improved performance and stability. \$\endgroup\$ Commented Nov 3, 2020 at 17:48
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The default DDR3 topology is fly-by with VTT endpoint termination. This topology is easy to route, performant, safe and reliable. It has all the advantages, except one: The VTT termination resistors consume a bit of extra power.

If you only have a single DDR3 memory die, then you can often use point-to-point topology without VTT termination to reduce power consumption. But this has to be validated on a case by case basis.

If you have two DDR3 dies, then unterminated T-topology is a often a viable low power option. But again, it has to be validated on a case by case basis.

With 4 or more dies, T-topology typically becomes too complicated to be worth it. You should use fly-by.

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  • \$\begingroup\$ Validate on case by case basis, how? \$\endgroup\$
    – quantum231
    Commented May 24, 2022 at 9:12
  • \$\begingroup\$ Signal quality verification using a high-bandwidth oscilloscope. Ideally with a DDR3 compliance test plugin. \$\endgroup\$ Commented May 27, 2022 at 22:08
  • \$\begingroup\$ "DDR3 compliance test plugin", what is that? How high should the bandwidth be? 1GHz, 10GHz? We also need to remember that there is a relationship between the probe and the scope bandwidths which lower the overall bandwidth. The probes need to be active or differential? \$\endgroup\$
    – quantum231
    Commented Jun 19, 2022 at 22:26
  • \$\begingroup\$ DDR3 compliance test plugin is a software plugin for your oscilloscope. Bandwidth requirement depends a bit on the DDR3 clock frequency, perhaps roughly 10x the DDR3 clock frequency. You need active differential solder-in probes. \$\endgroup\$ Commented Jun 19, 2022 at 23:38
  • \$\begingroup\$ I see, now a problem is that we can't put studs on high speed tracks, also DDR3 RAM will likely use a BGA package so no access to all pins on the PCB to its pads directly. Now where does a person even use the scope probe? I mean we would need to see all the data and control lines along with the clock. However, I don't see this has being possible! \$\endgroup\$
    – quantum231
    Commented Jun 20, 2022 at 1:12

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