In GPUs/CPUs, are FPUs made up of ALUs? If not, what would be a smaller "logical unit" that FPUs are made up of? If FPUs are made up of ALUs, how many ALUs would it take to make up a 16-bit FPU? 32-bit FPU? 64-bit-FPU? Also, correct me if I'm completely not understanding the make-up of FPUs correctly. I'm a bit confused about this topic, and I've only studied how ALUs function, so I may be understanding this concept completely wrong.
ALUs and FPUs are grossly made of the same building blocks : Adders/subtractors, multipliers, bit shifters, multiplexers...
It's just that they are organised very differently and have different widths. As FP operations are more complex, in a CPU, the FPU is usually larger than the ALU.
- Some processors, particularly DSPs and GPUs use the same hardware for integer and floating point instructions
- There are in modern CPUs several ALUs in parallel, they are able to execute more integer than floating point instructions per cycle.
- FPUs are now very, very complex and large due to the addition of SIMD instructions (MMX/AVX/SSE/NEON...).
ALU means "Arithmetic Logic Unit" historically as wiki said, "performs arithmetic and bitwise operations on integer binary numbers."
In fact, FPU added to CPU as external IC in old design today they called "Execution unit".
BUT some DSP chips have internal FPU implementation some have both fixed and floating instruction.
In some cores, Cortex-M FPU for example, FPU is inserted as an optional module. So if it present and you put some data on some dedicated register and send a command to a module that module can handle floating-point processing.
You might find this Masters thesis relevant.
The student synthesized and simulated a 64-bit ALU and simple 64-bit FPU (only basic operations, no trig or exponential functions) in TSMC’s 130nm process.
Both were of the order of 100,000 gates, but the ALU actually ended up about 45% more complex than the FPU. I assume that’s in part because of the 128-bit multiplier output, and fewer mantissa bits required for the mantissa in the FPU. For maximum performance, the complexity increases much faster than linear with the number of bits.
A commercial FPU design such as the optional single or double precision FPU available in some ARM chips would be more capable and probably more complex.