# 100Mhz damped Sine Wave

I have simulated an damped sine wave generator in ltspice. Since I couldn't find a model for single pole double throw relay, I used two switch. It is very basic circuit first charges capacitor and with simultaneous switching oscilates with inductor.

For frequencies up to 10Mhz it works well. But for 100Mhz wave shape got distorted.

As it seen in the picture First cycle is smaller than the second one. This is in LTspice. In real life it is much more weird: For first 3 consecutive cycle voltage goes up. After 4th or 5th cycle it oscilates as normal damped sine wave as I would expect it to be.

When I double the value of inductor and half the value of capacitor signal gets better. But this time Q(it should be at least 10) factor decreases.

My purpose is to have a normal 100MHz damped sine wave. Not like in the picture(in the picture it goes up and then down).

How to deal with this problem?.

• Hi, it's "MHz", not "Mhz", by the way. The unit is Hz. – Marcus Müller Nov 5 '20 at 11:20
• Is S1 truly a short or is there some series resistance inside it that dominates thus making it more like a series tuned circuit. Just because it looks like a parallel circuit, doesn't mean it behaves like one. – Andy aka Nov 5 '20 at 11:34
• Why do you say "underdamped"? To me, each cycle looks like a damped sinewave.... – LvW Nov 5 '20 at 12:00
• Agian: What is your goal? To produce a sequence of damped sinus signals? – LvW Nov 5 '20 at 14:28
• @Ismail So, in the end, what exactly is the problem: that you can't match the response as in real life, or that you can't match the real life with the simulation? Or you expected something but got something else? If you did, what is it? And where, simulation or real life? Please don't make us keep on asking, it's you who has to explain so that an answer can be given. All you're saying is that the first cycles are smaller, that the real life is similar, and ask how to deal with the problem. But nobody can understand the problem if you're not stating it. Also, try to show the whole schematic. – a concerned citizen Nov 5 '20 at 19:40

This is a concept showing the oscillations across the parallel RLC tank in the drain of M1. The transistor can be any kind, as long as it can switch very abruptly. Here, I've chosen one from the database that's suppose to have 1.7 nC gate charge and 0.17 Ω on-resistance, in order for the gate signals to make switching times sharp. If you look at the drain current, you can see that in the simulation (at least) it can switch in around 11 ns, which means that for a 100 MHz sine oscillation, the fist period would be affected. The faster it can switch, the better the initial period.
In the picture above, there is also a switch configured to be an ideal switch, i.e. there is no soft transition, which means that V(c,d) is the ideal representation of what such a circuit might show. Compare that voltage with V(a,b), and if you find that unsatisfactory, then the problem you'll need to solve has nothing to do with simulation or building the circuit.