# Logical OR vs Logical Addition

According to this tutorial on Exclusive-OR Gate

The logic or Boolean expression given for a logic OR gate is that for Logical Addition which is denoted by a plus sign, (+).

However, in my understanding

1 OR 1 =1

1 + 1 = 0 (1 carryover)

How come that logical OR is the same as logical addition?

• logical addition is not arithmetic addition ... in fact, the + still means OR – jsotola Nov 6 '20 at 1:16
• This possibly answers your question: electronics.stackexchange.com/questions/131317/… – Lars Hankeln Nov 6 '20 at 7:51
• Is that quote from that page? Because I can't find it there. – ilkkachu Nov 6 '20 at 11:57
• @ilkkachu I just fixed the link! Thanks for catching! – YumekaMengjiaLYU Nov 6 '20 at 22:26

## 2 Answers

The + operator has different meaning depending on the operands (1 and 1 in your case), e.g.:

• Decimal numbers: 1 + 1 = 2 (decimal), where + means decimal addition
• Binary numbers: 1 + 1 = 10 (1 is carried over for 1 bit), where + means binary addition
• Logical / Boolean: 1 + 1 = 1, where + means logical OR
• Text: "abc" + "def", where + means text concatenation
• Array/Lists: [1, 2] + [3, 4] = [1, 2, 3, 4], where + means list concatenation

Actually, + can be defined depending on the context, where the first three examples are assumed trivial, and the last two can be used in some programming languages, all using the same '+' sign/operator to denote different functions/meanings.

• Thanks! Very clear explanation : ) – YumekaMengjiaLYU Nov 6 '20 at 23:43

That site is a bit confused in its syntax use.

Let’s make this clear: ‘+’ means arithmetic addition. A sum of two one-bit numbers produces one sum bit and one carry. This is called a half-adder. A full adder extends this to include a carry-in bit.

Anyway, In logic, a one-bit half-adder is a XOR function for sum and OR for the carry. That is, for an adder with inputs a and b:

• sum = a XOR b
• carry = a AND b

Ancient History

Some primitive logic design languages used the ‘+’ symbol for OR and ‘*’ symbol for AND. When I say ‘primitive’, I mean really old, obsolete design entry methods like PALASM (c. 1976 or so) and some early university-developed tools.

This isn’t the case anymore. Modern hardware description languages don’t use arithmetic symbols for logic operators.

Verilog uses bar and ampersand symbols for OR and AND logicals, similar to the C language:

• ‘|’ (vertical bar) for bitwise OR
• ‘||’ for logical OR
• ‘&’ (ampersand) for bitwise AND
• ‘&&’ for logical AND

VHDL uses keywords ‘or’, ‘and’, ‘xor’, etc. for logic ops.

In both VHDL and Verilog, ‘+’ and ‘*’ are only for arithmetic.

And now, that half-adder in Verilog:

• sum = a ^ b; // exclusive-or
• carry = a && b; // OR