That site is a bit confused in its syntax use.
Let’s make this clear: ‘+’ means arithmetic addition. A sum of two one-bit numbers produces one sum bit and one carry. This is called a half-adder. A full adder extends this to include a carry-in bit.
Anyway, In logic, a one-bit half-adder is a XOR function for sum and OR for the carry. That is, for an adder with inputs a and b:
- sum = a XOR b
- carry = a AND b
Some primitive logic design languages used the ‘+’ symbol for OR and ‘*’ symbol for AND. When I say ‘primitive’, I mean really old, obsolete design entry methods like PALASM (c. 1976 or so) and some early university-developed tools.
This isn’t the case anymore. Modern hardware description languages don’t use arithmetic symbols for logic operators.
Verilog uses bar and ampersand symbols for OR and AND logicals, similar to the C language:
- ‘|’ (vertical bar) for bitwise OR
- ‘||’ for logical OR
- ‘&’ (ampersand) for bitwise AND
- ‘&&’ for logical AND
VHDL uses keywords ‘or’, ‘and’, ‘xor’, etc. for logic ops.
In both VHDL and Verilog, ‘+’ and ‘*’ are only for arithmetic.
And now, that half-adder in Verilog:
- sum = a ^ b; // exclusive-or
- carry = a && b; // OR