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I am using a LDO with a SOT-223 footprint and since it might get hot, I wanted to make a nice thermal pad under it to dissipate that heat. I googled and I only found thermal pads, but i wanted some guidelines on thermal vias to dissipate the heat to other layers. Could some one please give me some reading material? I want to know how far to place the vias from each other, how many vias to use and the size of them.

EDIT: The part is the MCP1703 but I think this question is more related to the footprint than the part itself

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  • \$\begingroup\$ The more vias the better. Larger vias (at least 8 - 10 mil) are generally preferred. \$\endgroup\$ – The Photon Jan 6 '13 at 4:56
  • \$\begingroup\$ First thing you want to look at is the datasheet for the ldo itself. I know TI's tend to give good info on the suggested footprints. \$\endgroup\$ – Passerby Jan 6 '13 at 12:47
  • \$\begingroup\$ There is nothing on the datasheet \$\endgroup\$ – mFeinstein Jan 7 '13 at 4:40
  • \$\begingroup\$ But more vias is less copper plane...so which one is ther better? \$\endgroup\$ – mFeinstein Jan 7 '13 at 4:40
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First, a couple of the answers (at least on the first draft) seem to have confused SOT-223 with SOT-23. SOT-23 is a very small packaged designed more for small size than for heat dissipation. SOT-223 is also quite small, but does have a substantial thermal tab:

enter image description here

Sources differ on the actual thermal properties of SOT-223. The TI app note AN-1028 cited by Garrett gives a junction-to-ambient thermal resistance (\$\theta_{JC}\$) of 12 C/W. The Microchip app note AN792 also cited in Garrett's answer gives 57 C/W. Another TI datasheet, for the TLV1117, gives 104 C/W.

The main reason for this discrepency is that the thermal resistance depends not just on the package, but on the size of the copper pads available to serve as a heat sink for the part, as shown in this graph taken from the TI app note:

enter image description here

The 12 C/W number is apparently the asymptotic limit of this curve. Note that it requires 2 oz copper and probably 2 in2 or more of copper area to achieve that value.

To finally get to your question, how to lay out the heat sink pad, in roughly decreasing importance:

  • The larger the pad you can fit in your design the better.
  • Heavier copper is better (e.g., 2 oz rather than 1 oz copper).
  • When connecting through to a thermal pad on the opposite side of the board, use many vias. As a rule of thumb, I'd recommend spacing vias on a 50 mil grid or so, over the whole pad area.
  • Use vias larger than the minimum size. As a rule of thumb I'd try to use at least 8 mil via diameter and use 10 to 18 mil by preference. Extremely large vias, of course, end up reducing the pad area, so there's a limit to how large you want to go.
  • Place the heat-generating part as close to the center of the thermal pad as possible.

Finally, in contrast to the suggestion in another answer, I would do my design this way:

  • Determine the input and output voltages of your regulator, and the operating current. From this determine the power requirement.

  • Determine the maximum ambient temperature where your circuit will operate.

  • Determine the maximum junction temperature you can operate at. Typically this is 125 C in the datasheet, but you may want to de-rate by 25 C or more to give design margin and improve reliability.

  • Now choose a package and design a layout that allows you to meet your maximum operating junction temperature.

In particular, it is not possible to determine the temperature rise until after you've chosen a package.

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Can you post the part?

The best advice I can offer is first to understand that LDO dissipation is simply related to (Vin-Vout) * Iout, where Vin is the input voltage, Vout is the output voltage and Iout is the output current. In general, you shouldn't need to worry too much for less than 500mA. However, you can take the datasheet of the LDO and look at the thermal resistance. This tells you exactly what will be the temperature rise given a certain wattage dissipation. You can calculate the dissipation with the formula above. For example LM7805 has 5 degrees per watt. So, you can expect a rise of 5 degrees for every watt you calculate it dissipates.

So, what I would do if I were you is:

1) Calculate the expected wattage dissipation. Be conservative.

2) Calculate the expected temperature rise. Anything 40-50 degrees is likely not an issue at all. Close to 90 degrees and over you almost have to take care of it.

3) Pick the right package. Different parts have different packages, each with different thermal resistance. Usually larger packages and those with tabs for power dissipation have lower resistance, hence they will heat less. If the temperature is not acceptable,you might need to pick another part.

Look at the following video from Dave at EEVblog. Dave does an awesome job at explaining all the terms and how to do the design. Should cover all you need.

Specifically to address your vias, clearly more vias enable more heat to be sinked to other plans and hence increase the heatsink, but it's important to know how much area you need. Datasheets often recommend the area in mm^2 required for certain thermal resistance.

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Very good question and a often overlooked one. SOT-223 devices do not dissipate heat very well so you do need to pay extra attention to the design, and make sure you have enough room to dissipate some of the heat the device creates. Do not put via's on the pads, as these will suck up some of the solder when you are mounting the device and may cause it to not make good contact with the pad. Also try to keep the spacing between the vias even and make sure the area you are diverting this heat to can handle it and it won't adversely effect other items nearby.

Could some one please give me some reading material?

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    \$\begingroup\$ SOT-223 is not the same as SOT-23. As shown in your second linked doc, SOT-23 has Theta-ja of 250-350 C/W, while SOT-223 is about 60 C/W. Saying "SOT-223 devices do not dissipate heat very well" is overgeneralizing. Sometimes you need 10 C/W. Sometimes you only need 60 C/W. Sometimes you only need 300 C/W. It would be foolish to restrict yourself to an oversized D-PAK package in a situation where a SOT-223 is adequate. \$\endgroup\$ – The Photon Jan 6 '13 at 18:47
  • \$\begingroup\$ As I said...I cant find any Application Notes that has vias examples...I already have seen these ones...just pads examples...no vias \$\endgroup\$ – mFeinstein Jan 7 '13 at 4:46

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