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I am porting a working sequential circuit from a DE0-Nano to a DE5-Net. The circuit is driven by one global 50 MHz clock signal. The circuit only has one input and one output port for serial communication.

The VHDL of my circuit is generated and I don't know how to interpret the DE5-Net documentation. I've done some preparatory work on the pin assignments and would appreciate if somebody can confirm my "choices" of the pin assignments are correct. I also need to know the pin name of the 50 MHz clock.

The ports of my top entity (DE5-Net) are as follows:

  • clock (50 MHz input bit; Pin ??)

  • reset (input bit: button 0; Pin AK15?)

  • RX (input bit; Pin AE18?)

  • TX (output bit; Pin AE17?)

  • REn (output bit: always 0?; Pin AF17?)

  • DE (output bit: always 1?; Pin AG14?)

  • TE (output bit: always 0?; Pin AF16?)

My Quartus compiler accepts the VHDL and pin settings, but I need some confirmation my choices are correct.

FWIW I understand there are more efficient ways to do the communication, but I first want to get a working single bit version.

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In the DE5-Net CD you can find several files for pin assignment. For instance the .qsf file in one of the demonstrations projects.

Instead of manually assigning pins you can import the .qsf file in Assignments>ImportAssignment of Quartus and then you can eventually rectify the name either in your VHDL/Verilog or in the Pin Planner of Quartus.

You can find for instance several duplication of the 50MHz clock:

set_location_assignment PIN_AW35 -to OSC_50_B3B
set_location_assignment PIN_BC28 -to OSC_50_B3D
set_location_assignment PIN_AP10 -to OSC_50_B4A
set_location_assignment PIN_AY18 -to OSC_50_B4D
set_location_assignment PIN_M8 -to OSC_50_B7A
set_location_assignment PIN_J18 -to OSC_50_B7D
set_location_assignment PIN_R36 -to OSC_50_B8A
set_location_assignment PIN_R25 -to OSC_50_B8D

For button[0] you can find the following;

set_location_assignment PIN_AK15 -to BUTTON[0]

You can assign other pins by editing .qsf file as I mentioned:

set_location_assignment PIN_AG14 -to RS422_DE
set_location_assignment PIN_AE18 -to RS422_DIN
set_location_assignment PIN_AE17 -to RS422_DOUT
set_location_assignment PIN_AF17 -to RS422_RE_n
set_location_assignment PIN_AF16 -to RS422_TE
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  • \$\begingroup\$ Thanks @paul-ghobril I know about the .qsf file and how to use it. I don't know about the pin names. That's what the question is about. \$\endgroup\$
    – Joey
    Nov 7 '20 at 18:57
  • \$\begingroup\$ If you are saying that PIN_AW35 is a valid pin name for a 50 MHz clock signal then that almost answers my question. If you can confirm the other names I mention are valid, then that'll be perfect. \$\endgroup\$
    – Joey
    Nov 7 '20 at 19:00
  • \$\begingroup\$ @Joey I edited and completed the list. \$\endgroup\$ Nov 7 '20 at 19:18
  • \$\begingroup\$ Thanks @paul-ghobril. I'll try the settings. I am waiting for some component parts before I can actually program FPGA. I may get back if there are problems (but probably not needed). Thanks again. \$\endgroup\$
    – Joey
    Nov 7 '20 at 19:20

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